Abstract
The detection of catastrophic short and open faults in bipolar current mode logic (CML) circuits is studied. The non-intrusive tests considered include functional (logic) tests, an Idd test, and a common-mode test. A 622 Mbps SONET SIPO (Serial-In/Parallel-Out) and a PISO (Parallel-In/Serial-Out) circuit form the basis of this case study.
Similar content being viewed by others
References
E. Kofi-Vida Torku, A. Parise, and R.K. Gaede, “Modeling of Bipolar DCS DOT Circuits,” in Proc. IEEE Midwest Symp. on Circuits and Systems, 1992, pp. 1124–1127.
E. KofiVida-Torku, W. Reohr, J.A. Monzel, and P. Nigh, “Bipolar, CMOS, and BiCMOS Circuit Technologies Examined for Testability,” in Proc. IEEE Symp. Midwest Circuits and Systems, 1991, pp. 1015–1020.
S.M. Menon, A.P. Jayasuma, and Y.K. Malaiya, “Fault Modeling of ECL Devices,” Electronic Letters, Vol. 26, No. 15, pp. 1105–1108, July 1990.
S. Hessabi, M.Y. Osman, M.I. Elmasry, “Differential BiCMOS Logic Circuits: Fault Characterization and Design for Testability,” IEEE Trans. on VLSI Systems, Vol. 3, No. 3, pp. 437–445, Sept. 1995.
V. Devdas, “Fault Characterization and Testing of Digital Current Mode Logic Circuits”, M.A.Sc. Thesis, The University of British Columbia, April 1999.
Rights and permissions
About this article
Cite this article
Ivanov, A., Devdas, V. Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study. Journal of Electronic Testing 16, 631–634 (2000). https://doi.org/10.1023/A:1008325420970
Issue Date:
DOI: https://doi.org/10.1023/A:1008325420970