Abstract
This paper presents a High-Level EDA environment based on the Hierarchical Distributed BIST (HD-BIST), a flexible and reusable approach to solve BIST scheduling issues in System-on-Chip applications. HD-BIST allows activating and controlling different BISTed blocks at different levels of hierarchy, with a minimum overhead in terms of area and test time. Besides the hardware layer, the authors present the HD-BIST application layer, where a simple modeling language, and a prototypical EDA tool demonstrate the effectiveness of the automation of the HD-BIST insertion in the test strategy definition of a complex System-on-Chip.
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Benso, A., Cataldo, S., Chiusano, S. et al. A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. Journal of Electronic Testing 16, 179–184 (2000). https://doi.org/10.1023/A:1008326928340
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DOI: https://doi.org/10.1023/A:1008326928340