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A Practical Vector Restoration Technique for Large Sequential Circuits

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Abstract

Given a test sequence and a list of faults detected by the sequence, vector restoration techniques extract a minimal subsequence that detects a chosen subset of modeled faults. Vector restoration techniques are useful in static compaction of test sequences and in fault diagnosis. We propose a new vector restoration technique that is a significant improvement over the state of the art in several ways: (1) a sequence of length n can be restored with only O(n log 2 n) simulations while known approaches require simulation of O(n 2) vectors, (2) a two-step restoration process is used that makes vector restoration practical for large designs, and (3) restoration process for several faults is overlapped to provide significant acceleration in vector restoration. Our new ideas can be used to improve run-times of known static compaction and fault diagnosis methods. We integrated the proposed vector restoration technique into a static test sequence compaction system. Our experiments show that the new restoration technique, as compared to known techniques (Proceedings of Int. Conf. on Computer Design, University of Iowa, Aug. 1997, pp. 360–365.), is (1) about 2 times faster for the ISCAS benchmark circuits, and (2) 3 to 5 times faster on large, industrial designs. Using the new restoration technique, we successfully processed large industrial designs that could not be handled by earlier techniques (Proceedings of Int. Conf. on Computer Design, University of Iowa, Aug. 1997, pp. 360–365.) in 2 CPU days.

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References

  1. T.M. Niermann, R.K. Roy, J.H. Patel, and J.A. Abraham, “Test Compaction for Sequential Circuits,” IEEE Trans. Computer-Aided Design, Vol. 11, No. 2, pp. 260-267, Feb. 1992.

    Google Scholar 

  2. B. So, “Time-Efficient Automatic Test Pattern Generation System,” Ph.D. Thesis, EE Dept., Univ. of Wisconsin at Madison, 1994.

    Google Scholar 

  3. I. Pomeranz and S.M. Reddy, “On Static Compaction of Test Sequences for Synchronous Sequential Circuits,” Proc. Design Automation Conf., June 1996, pp. 215-220.

  4. M.S. Hsiao, F.M. Rudnick, and J.H. Patel, “Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors,” Proc. IEEE VLSI Test Symp., Apr. 1995, pp. 188-195.

  5. M.S. Hsiao and S.T. Chakradhar, “Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits,” Technical Report 1997, Computers & Communications Research Lab, NEC USA Inc.

  6. R. Guo, I. Pomeranz, and S.M. Reddy, “Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration,” Technical Report 8-3-1997, Electrical and Computer Engineering Department, University of Iowa, 1997.

  7. I. Pomeranz, and S.M. Reddy, “Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits,” in Proceedings Int. Conf. on Computer Design, 1997. University of Iowa, Aug. 1997, pp. 360-365.

  8. F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,” Int. Symposium on Circuits and Systems, May 1989, pp. 1929-1934.

  9. T.M. Niermann and J.H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Conf. Design Automation (EDAC), March 1991, pp. 214-218.

  10. A. Raghunathan and S.T. Chakradhar, “Acceleration Techniques for Dynamic Vector Compaction,” Proc. Intl. Conf. Computer-Aided Design, Aug. 1995, pp. 310-317.

  11. S.T. Chakradhar and A. Raghunathan, “Bottleneck Removal Algorithm for Dynamic Compaction in Sequential Circuits,” IEEE Trans. on Computer-Aided Design, 1997, accepted for publication.

  12. T.M. Niermann and J.H. Patel, “Method for Automatically Generating Test Vectors for Digital Integrated Circuits,” U.S. Patent No. 5,377,197, Dec. 1994.

  13. M.S. Hsiao, E.M. Rudnick, and J.H. Patel, ”Sequential Circuit Test Generation Using Dynamic State Traversal,” Proc. European Design and Test Conf., Feb. 1997, pp. 22-28.

  14. E.M. Rudnick and J.H. Patel “Simulation-Based Techniques for Dynamic Test Sequence Compaction,” Proc. Intl. Conf. Computer-Aided Design, Nov. 1996, pp. 67-73.

  15. T.J. Lambert and K.K. Saluja, “Methods for Dynamic Test Vector Compaction in Sequential Test Generation,” in Proc. Int. Conf. on VLSI Design, Jan. 1996, pp. 166-169.

  16. I. Pomeranz and S.M. Reddy, “Dynamic Test Compaction for Synchronous Sequential Circuits Using Static Compaction Techniques,” in Proc. Fault-Tolerant Computing Symp., pp. 53-61, June 1996.

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Bommu, S.K., Doreswamy, K.B. & Chakradhar, S.T. A Practical Vector Restoration Technique for Large Sequential Circuits. Journal of Electronic Testing 16, 521–539 (2000). https://doi.org/10.1023/A:1008329018664

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