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Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS

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Abstract

It is important to predict noise at the early stages of a top-down design. In this paper, we propose a methodology to model phase noise or jitter, a key specification for phase-locked loops, using a mixed-signal hardware description language, and to simulate the effects of catastrophic faults on the phase jitter at the behavioral level. In contrast to existing approaches which either require dedicated noise simulators or postpone noise and fault simulation to the transistor level, we have successfully demonstrated that noise in a voltage-controlled oscillator (VCO), power supply noise, and their effects on the overall phase jitter within a faulty PLL can be modeled and simulated earlier on at the behavioral level. Our simulation results are consistent with experimentally-verified theoretical predictions.

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Authors and Affiliations

  1. Wireless Integrated Technology Center, Motorola, Ft. Lauderdale, FL, 33322

    Nihal J. Godambe

  2. Department of Electrical Engineering, University of Washington, Seattle, WA, 98195

    C.-J. Richard Shi

Authors
  1. Nihal J. Godambe
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  2. C.-J. Richard Shi
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Godambe, N.J., Richard Shi, CJ. Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS. Journal of Electronic Testing 13, 7–17 (1998). https://doi.org/10.1023/A:1008329031457

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