Abstract
This paper presents a non-scan design-for-testability method for controllers that are synthesized from FSMs (Finite State Machines). The proposed method can achieve complete fault efficiency: test patterns for a combinational circuit of a controller are applied to the controller using state transitions of the FSM. In the proposed method, at-speed test application can be performed and the test application time is shorter than previous methods. Moreover, experimental results show the area overhead is low.
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Ohtake, S., Masuzawa, T. & Fujiwara, H. A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency. Journal of Electronic Testing 16, 553–566 (2000). https://doi.org/10.1023/A:1008333102734
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DOI: https://doi.org/10.1023/A:1008333102734