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On-Line Error Detection for Bit-Serial Multipliers in GF(2m)

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Abstract

In this paper error detection is applied to four finite field bit-serial multipliers. It is shown that by using parity prediction, on-line error detection can be incorporated into these multipliers with very low hardware overheads. These hardware overheads are generally independent of m and comprise only a handful of gates, so for large values of m these overheads are particularly low. The fault coverage of the presented structures has been investigated by simulation experiment and shown to range between 90% and 94.3%.

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Fenn, S., Gossel, M., Benaissa, M. et al. On-Line Error Detection for Bit-Serial Multipliers in GF(2m). Journal of Electronic Testing 13, 29–40 (1998). https://doi.org/10.1023/A:1008333132366

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  • DOI: https://doi.org/10.1023/A:1008333132366

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