Skip to main content
SpringerLink
Log in

Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles, both, data and control parts of the design in a uniform manner is proposed. The method combines deterministic and simulation-based techniques. On the register-transfer level, deterministic path activation is combined with simulation based-techniques used for constraints solving. The gate-level local test patterns for components are randomly generated driven by high-level constraints and partial path activation solutions. Experiments show that high fault coverages for circuits with complex sequential structures can be achieved in a very short time by using this approach.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. T.M. Niermann and J.H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Conf. Design Automation, 1991, pp. 214-218.

  2. M.S. Hiao, E.M. Rudnick, and J.H. Patel, “Sequential Circuit Test Generation Using Dynamic State Traversal,” Proc. European Design and Test Conf., 1997, pp. 22-28.

  3. F. Corno, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda, “GATTO:AGenetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits,” IEEE Trans. CAD, Vol. 15, pp. 991-1000, August 1996.

    Google Scholar 

  4. E.M. Rudnick, J.H. Patel, G.S. Greenstein, and T.M. Niermann, “Sequential Circuit Test Generation in a Genetic Algorithm Framework,” Proc. Design Automation Conf., 1994, pp. 698-704.

  5. J. Santucci, A. Courbois, and N. Giambiasi, “Behavioral Testing of Digital Circuits,” Journal of Microelectronics Systems Integration, Vol. 1, No. 1, pp. 55-77, 1993.

    Google Scholar 

  6. C.H. Cho and J.R. Armstrong, “B-Algorithm: A Behavioral Test Generation Algorithm,” Proc. Int. Test Conf., 1994, pp. 968-979.

  7. F. Ferrandi, F. Fummi, and D. Sciuto, “Implicit Test Generation for Behavioral VHDL Models,” Proc. Int. Test Conf., 1998, pp. 587-596.

  8. J. Lee and J.H. Patel, “Architectural Level Test Generation for Microprocessors,” IEEE Trans. CAD, Vol. 13, pp. 1288-1300, October 1994.

    Google Scholar 

  9. A. Ghosh, S. Devadas, and A.R. Newton, “Sequential Test Generation at the Register-Transfer and Logic Levels,” Proc. Design Automation Conf., 1990, pp. 580-586.

  10. B.T. Murray and J.P. Hayes, “Hierarchical Test Generation Using Precomputed Tests for Modules,” Proc. Int. Test Conf., 1998, pp. 221-229.

  11. R. Ubar, “Test Synthesis with Alternative Graphs,” IEEE Design & Test of Computers, pp. 48-57, Spring 1996.

  12. R. Ubar, “Multi-Valued Simulation of Digital Circuits with Structurally Synthesized Binary Decision Diagrams,” Journal Multiple Valued Logic, Vol. 4, pp. 141-157, 1998.

    Google Scholar 

  13. R. Ubar, “Test Generation for Digital Circuits Using Alternative Graphs,” Proc. of Tallinn Technical University, Estonia, No. 409, pp. 75-81 (in Russian), 1976.

  14. S.B. Akers, “Binary Decision Diagrams,” IEEE Trans. Computers, Vol. 27, pp. 509-516, June 1978.

    Google Scholar 

  15. H.-T. Liaw and C.-S. Lin, “On the OBDD-Representation of General Boolean Functions,” IEEE Trans. Computers, Vol. 41, pp. 661-664, June 1992.

    Google Scholar 

  16. S. Freeman, “Test Generation for Data Path Logic: The F-Path Method,” IEEE Journal Solid-State Circuits, Vol. 23, pp. 421-427, April 1988.

    Google Scholar 

  17. HLSynth92 benchmark directory at URL:http://www.cbl. ncsu.edu/pub/Benchmark_dirs/HLSynth92/

  18. E. Gramatova,M. Gulbins, M. Marzouki, A. Pataricza, R. Sheinauskas, and R. Ubar, “FUTEG Benchmarks,” Technical Report of project COPERNICUS JEP 9624 FUTEG No9/1995.

  19. G. Jervan, A. Markus, J. Raik, and R. Ubar, “DECIDER: A Decision Diagram based Hierarchical Test Generation System,” Proc. Design & Diagnostics of Electronic Circuits & Systems Workshop, 1998, pp. 269-273.

  20. J. Raik, and R. Ubar. “Sequential Circuit Test Generation Using Decision Diagram Models,” Proc. DATE Conf., 1999, pp. 736-740.

  21. G. Jervan, A. Markus, P. Paomets, J. Raik, and R. Ubar, “Turbo Tester: A CAD System for Teaching Digital Test,” Microelectronics Education, Kluwer Academic Publishers, Dordrecht, 1998, pp. 287-290.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Engineering, Tallinn Technical University, Raja 15, 12618, Tallinn, Estonia

    Jaan Raik & Raimund Ubar

Authors
  1. Jaan Raik
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Raimund Ubar
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Raik, J., Ubar, R. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Journal of Electronic Testing 16, 213–226 (2000). https://doi.org/10.1023/A:1008335130158

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1008335130158

Search

Navigation