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An Efficient Logic Equivalence Checker for Industrial Circuits

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Abstract

We present our formal combinational logic equivalence checking methods for industry-sized circuits. Our methods employ functional (OBDDs) algorithms for decisions on logic equivalence and structural (ATPG) algorithms to quickly identify inequivalence. The complimentary strengths of the two types of algorithms result in a significant reduction in CPU time. Our methods also involve analytical and empirical heuristics whose impact on performance for industrial designs is considerable. The combination of OBDDs, ATPG, and our heuristics resulted in a decrease in CPU time of up to 80% over OBDDs alone for the circuits we tested. In addition, we describe an algorithm for automatically determining the correspondence between storage elements in the designs being compared.

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Authors and Affiliations

  1. IBM, 11400 Burnet Road, MD 9460, Austin, TX, 78758, USA

    Jaehong Park

  2. Motorola Inc., 5918 West Courtyard Drive, Austin, TX, 78730, USA

    Carl Pixley & Michael Burns

  3. Samsung Electronics Inc., Kihung, Kyungi-do, Korea

    Hyunwoo Cho

Authors
  1. Jaehong Park
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  2. Carl Pixley
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  3. Michael Burns
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  4. Hyunwoo Cho
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Park, J., Pixley, C., Burns, M. et al. An Efficient Logic Equivalence Checker for Industrial Circuits. Journal of Electronic Testing 16, 91–106 (2000). https://doi.org/10.1023/A:1008349024680

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