Abstract
Custom circuits, in contrast to those synthesized by automatic tools, are manually designed blocks of which the performance is critical to the full chip operation. Testing these blocks represents a major challenge and thus a crucial time-to-market factor in today's PowerPC microprocessor design environment. This paper investigates various methodologies for testing custom blocks. Issues of efficiently obtaining proper circuit models for ATPG tools as well as producing quality tests will be analyzed and discussed. Tradeoffs among various methods will be analyzed and compared. Experience and results based on recent PowerPC microprocessors will be reported.
Similar content being viewed by others
References
J. Park, M. Naivar, R. Kapur, M.R. Mercer, and T.W. Williams, “Limitations in Predicting Defect Level Based on Stuck-at Fault Coverage, ” Proc. VLSI Test Symposium, 1994.
P.C. Maxwell, R.C. Aitken, V. Johansen, and I. Chiang, “The Effectiveness of Iddq, Functional, and Scan Tests: How Many Fault Coverages Do We Need?, ” Proc. International Test Conference, 1992, pp. 168–177.
S.C. Ma, P. Franco, and E.J. McCluskey, “An Experimental Chip To Evaluate Test Techniques, Experiment Results, ” Proc. International Test Conference, 1995, pp. 663–672.
M.R. Grimaila et al., “REDO-Random Excitation and Deterministic Observation-First Commercial Experiment, ” Proc. VLSI Test Symposium, 1999.
Li-C. Wang, Ray Mercer, and T.W. Williams, “Using Target Faults To Detect Non-Target Defects, ” Proc. International Test Conference, 1996, pp. 629–638.
K.M. Bulter and M.R. Mercer, “Quantifying Non-Target Defect Detection by Target Fault Test Sets, ” Proc. European Test Conference, 1991, pp. 91–100.
N. Ganguly, M.S. Abadir, and M. Pandey, “PowerPC Array Verification Methodology Using Formal Verification Techniques, ” International Test Conference, Washington DC., 1996, pp. 857–864.
C.H. Malley and M. Dieudonne, “Logic Verification Methodology for PowerPC Microprocessors, ” 32nd Design Automation Conference, 1995, pp. 234–240.
C.J.H. Seger and R.E. Bryant, “Formal Verification By Symbolic Evaluation of Partially-Ordered Trajectories, ” Formal Methods in System Design, Vol. 6, pp. 147–189, 1995.
R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang, “MIS: A Multiple-Level Logic Optimization System, ” IEEE Trans. on CAD, Vol. 6, pp. 1062–1081, Nov. 1987.
M.J. Batek and J.P. Hayes, “Test-Set Preserving Logic Transformations, ” Proc. 29th Design Automation Conference, 1992, pp. 454–457.
M.J. Bryan, S. Devadas, and K.Keutzer, “Testability-Preserving Circuit Transformations, ” Proc. ICCAD, 1990, pp. 456–459.
R.E. Bryant, “Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis, ” Proc. ICCAD, 1991, pp. 350–353.
R.E. Bryant, “Boolean Analysis of MOS Circuits, ” IEEE Trans. on CAD, July 1992, pp. 434–469.
K.J. Singh and P.A. Subrahmanyam, “Extracting RTL Models from Transistor Netlists, ” Proc. ICCAD, 1995, pp. 11–17.
S. Kundu, “GateMaker: A Translator to Gate Level Model Extractor for Simulation, Automatic Test Pattern Generation, and Verification, ” Proc. International Test Conference, 1998, pp. 372–381.
E.B. Eichelberger et al., Structured Logic Testing, Prentice Hall, 1991, Sec. 15.
C. Pyron, J. Prado, and J. Golab, “Next Generation PowerPC Microprocessor Test Strategy Improvements, ” Proc. International Test Conference, 1997, pp. 414–423.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Wang, LC., Abadir, M.S. On Efficiently Producing Quality Tests for Custom Circuits in PowerPC™ Microprocessors. Journal of Electronic Testing 16, 121–130 (2000). https://doi.org/10.1023/A:1008353109659
Issue Date:
DOI: https://doi.org/10.1023/A:1008353109659