Abstract
Test and validation of embedded array blocks remains a major challenge in today's microprocessor design environment. The difficulty comes from twofold, the sizes of the arrays and the complexity of their timing and control. This paper describes a novel test generation methodology for test and validation of microprocessor embedded arrays. Unlike traditional ATPG methods, our test generation method is based upon the high-level assertion specification which is originally used for the purpose of formal verification. The superiority of these assertion tests over the traditional ATPG tests will be discussed and shown through various experiments on recent PowerPC microprocessor designs.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Li-C. Wang and M.S. Abadir, “A New Validation Methodology Combining both Test and Formal Verification for PowerPC™ Microprocessor Arrays,” Proc. International Test Conference, 1997, pp. 954–963.
M. Pandey, R. Raimi, D.L. Beatty, and R.E. Bryant, “Formal Verification of PowerPC™ Arrays using Symbolic Trajectory Evaluation,” Proc. 33rd Design Automation Conference, 1996.
C.J.H. Seger and R.E. Bryant, “Formal Verification by Symbolic Evaluation of Partially—Ordered Trajectories,” Formal Methods in System Design, Vol. 6, pp. 147–189, 1995.
PowerPC™ 603e RISC Microprocessor User's Manual, Motorola Semiconductor Technical Data 1995.
C.H. Malley and M. Dieudonne, “Logic Verification Methodology for PowerPC Microprocessors,” 32nd Design Automation Conference, 1995, pp. 234–240.
N. Ganguly, M.S. Abadir, and M. Pandey, “PowerPC Array Verification Methodology using Formal Verification Techniques,” Proc. International Test Conference, 1996, pp. 857–864.
R.E. Bryant, “A Switch—Level Model and Simulator for MOS Digital Systems,” IEEE Transactions on Computers, Vol. C-33, No. 2, pp. 160–177, Feb. 1984.
C. Hunter, J. Slaton, J. Eno, R. Jessani, and C. Dietz, “The PowerPC603(tm) Microprocessor: An Array Built-In Self Test Mechanism,” Proc. International Test Conference, 1994, pp. 388–394.
R.E. Bryant, “Symbolic Simulation—Techniques and Applications,” 27th Design Automation Conference, 1990.
R.E. Bryant, “Symbolic Boolean Manipulation with Ordered Binary Decision Diagrams,” ACM Computing Surveys, Vol. 24, No. 3, Sept. 1992.
M. Pandey, R. Raimi, R.E. Bryant, and M.S. Abadir, “Formal Verification of Content Addressable Memories using Symbolic Trajectory Evaluation,” Proc. 34rd Design Automation Conference, 1997.
C.J.H. Seger, “Voss—A Formal Hardware Verification System: User's Guide,” Technical Report 93–45, Department of Computer Science, University of British Columbia, 1993.
M.S. Abadir and H.K. Reghbati, “Testing of Random Access Memories,” ACM Computing Surveys, Sept. 1983.
M.S. Abadir, J. Ferguson, and T.E. Kirkland, “Logic Design Verification via Test Generation,” IEEE Transactions on Computer—Aided Design, Vol. 7, No. 1, Jan. 1988.
Li-C. Wang, M.S. Abadir, and J. Zeng, “On Logic and Transistor Level Design Error Detection of Various Validation Methods for PowerPC™ Microprocessor Arrays,” Proc. VLSI Test Symposium, 1998, pp. 260–265.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Wang, LC., Abadir, M.S. Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays. Journal of Electronic Testing 13, 121–135 (1998). https://doi.org/10.1023/A:1008353704141
Issue Date:
DOI: https://doi.org/10.1023/A:1008353704141