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Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability

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Abstract

This research applies formal dataflow analysis and techniques to high-level DFT. Our proposed approach improves testability of the behavioral-level circuit description (such as in VHDL) based on propagation of the value ranges of variables through the circuit's Control-Data Flow Graph (CDFG). The resulting testable circuit is accomplished via controllability and observability computations from these value ranges and insertion of appropriate testability enhancements, while keeping the design area-performance overhead to a minimum.

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References

  1. S. Bhatia and N.K. Jha, “Genesis: A Behavioral Synthesis System for Hierarchical Testability, ” Proc. European Design and Test Conf., 1994, pp. 272–276.

  2. P.S. Parikh and M. Abramovici, “Testability-Based Partial Scan Analysis, ” Journal of Electronic Testing: Theory and Applications, Vol. 7, pp. 61–70, Aug. 1995.

    Google Scholar 

  3. S.T. Chakradhar, A. Balakrishnan, and V.D. Agrawal, “An Exact Algorithm for Selecting Partial Scan Flip-Flops, ” Proc. Design Automation Conf., 1994, pp. 81–86.

  4. M.S. Hsiao, G.S. Saund, E.M. Rudnick, and J.H. Patel, “Partial Scan Selection Based on Dynamic Reachability and Observability Information, ” Proc. Intl. Conf. VLSI Design, 1998, pp. 174–180.

  5. I. Ghosh, A. Raghunathan, and N.K. Jha, “Design for Hierarchical Testability of RTL Circuits Obtained by Behavioral Synthesis, ” Proc. Intl. Conf. Computer Design, 1995, pp. 173–179.

  6. S. Bhatia and N.K. Jha, “Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches, ” Proc. Intl. Conf. on Computer Design, 1994, pp. 91–96.

  7. T.C. Lee, N.K. Jha, and W.H. Wolf, “Behavioral Synthesis of Highly Testable Data Paths Under Non-Scan and Partial-Scan Environments, ” Proc. Design Automation Conf., 1993, pp. 292–297.

  8. F.F. Hsu, E.M. Rudnick, and J.H. Patel, “Enhancing High-Level Control-Flow for Improved Testability, ” Proc. Intl. Conf. Computer-Aided Design, 1996, pp. 322–328.

  9. N. Mukherjee, M. Kasab, J. Rajshi, and J. Tyszer, “Arithmetic Built-In Self Test for High-Level Synthesis, ” IEEE VLSI Test Symposium, 1995, pp. 132–139.

  10. M. Takahashi, R. Sakurai, H. Noda, T. Kambe, “A Testability Analysis Method for Register-Transfer Level Description, ” Proc. ASP-Design Automation Conf., 1997, pp. 307–312.

  11. F.F. Hsu, “High-Level Testability Analysis and Enhancement for Digital Systems, ” Ph.D. Dissertation, Univ. of Illinois at Urbana-Champaign, Oct. 1998.

    Google Scholar 

  12. K.A. Ockunzzi and C.A. Papachristou, “Testability Enhancement for Behavioral Descriptions Containing Conditional Statements, ” Proc. Intl. Test Conf., 1997, pp. 236–245.

  13. J.R.C. Patterson, “Accurate Static Branch Prediction by Value Range Propagation, ” Proc. Conf. Programming Lang. Design and Implementation, 1995, pp. 67–78.

  14. M.N. Wegman and F.K. Zadeck, “Constant Propagation with Conditional Branches, ” ACM Trans. Programming Lang. & Systems, Vol. 13, No. 2, pp. 181–210, April 1991

    Google Scholar 

  15. R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman, and F.K. Zadeck, “Efficiently Computing SSA and the Control Dependence Graph, ” ACM Trans. on Programming Lang. & Systems, Vol. 13, No. 4, pp. 451–490, Oct. 1991.

    Google Scholar 

  16. K. Knobe and V. Sarkar, “Array SSA Form and its use in Parallelization, ” Proc. ACM SIGPLAN-SIGACT Symposium on Principles of Programming Lang., Jan. 1998, pp. 107–120.

  17. 1992 High-Level Synthesis Workshop Benchmarks, www.ics.uci.edu/pub/HLSynth92.

  18. 1995 High-Level Synthesis Workshop Benchmarks, www.ics.uci.edu/pub/HLSynth95.

  19. S. Ravi, G. Lakshminarayana, and N.K. Jha, “TAO: Regular Expression Based High-Level Testability Analysis and Optimization, ” Proc. Intl. Test Conf., 1998, pp. 331–340.

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Authors and Affiliations

  1. Mentor Graphics Corporation, Warren, NJ, USA

    Sandhya Seshadri

  2. Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ, USA

    Michael S. Hsiao

Authors
  1. Sandhya Seshadri
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  2. Michael S. Hsiao
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Seshadri, S., Hsiao, M.S. Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability. Journal of Electronic Testing 16, 131–145 (2000). https://doi.org/10.1023/A:1008357211476

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