Abstract
This research applies formal dataflow analysis and techniques to high-level DFT. Our proposed approach improves testability of the behavioral-level circuit description (such as in VHDL) based on propagation of the value ranges of variables through the circuit's Control-Data Flow Graph (CDFG). The resulting testable circuit is accomplished via controllability and observability computations from these value ranges and insertion of appropriate testability enhancements, while keeping the design area-performance overhead to a minimum.
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Seshadri, S., Hsiao, M.S. Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability. Journal of Electronic Testing 16, 131–145 (2000). https://doi.org/10.1023/A:1008357211476
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DOI: https://doi.org/10.1023/A:1008357211476