Abstract
This paper presents a diagnostic method based on differential IDDQprobabilistic signatures, inspired by telecommunications systems. The method and its unique features are described. Then, results from an IC monitor containing controllable faults show the capability of the method to diagnose actual activated faults, despite a strong experimental current standard variation. These results validate previous simulation procedures, which are applied to quantify effects not covered by the monitor experiment, that is, the effect of the load of a bridged node and the effect of the bridge resistance value. These experimental and simulation results reveal the robustness of the proposed diagnosis method, that has identified and located every single fault considered so far.
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IEEE Test Technology Technical Committee, “A D&T Roundtable: Deep-Submicron Test,” IEEE Design & Test of Computers, Vol. 13, No. 3, pp. 102-108, Fall 1996.
E. Isern and J. Figueras, “IDDQ Test and Diagnosis of CMOS Circuits,” IEEE Design & Test of Computers, Vol. 12, No. 4, pp. 60-67, Winter 1995.
R.C. Aitken, “Diagnosis of Leakage Faults with IDDQ,” J. Electronic Testing: Theory and Applications, Vol. 3, No. 4, pp. 367-376, Dec. 1992.
R.C. Aitken, “Faults Location with Current Monitoring,” Int'l Test Conf., 1991, pp. 623-623.
J.M. Soden and R.E. Anderson, “IC Failure Analysis: Techniques and Tool for Quality and Reliability Improvement,” Proc. IEEE, Vol. 81, No. 5, pp. 703-715, May 1994.
T. Lee et al., “Circuit-Level Dictionaries of CMOS Bridging Faults,” IEEE VLSI Test Symp., 1994, pp. 386-391.
J.A. Waicukauski and E. Lindbloom, “Failure Diagnosis of Structured VLSI,” IEEE Design & Test of Computers, Vol. 6, No. 4, pp. 49-60, Fall 1989.
S. Chakravarty and M. Liu, “Algorithms for IDDQ Measurement Based Diagnosis of Bridging Faults,” J. Electronic Testing: Theory and Applications, Vol. 3, No. 4, pp. 377-386, Dec. 1992.
J.M. Soden, C.F. Hawkins, and A.C. Miller, “Identifying Defects in Deep-SubmicronCMOSICs,” IEEE Spectrum,Vol. 33, No. 9, pp. 66-71, Sept. 1996.
S.P. Athan, D.L. Landis, and S.A. Al-Arain, “A Novel Builtin Current Sensor for IDDQ Testing of Deep Submicron CMOS ICs,” IEEE VLSI Test Symp., 1996, pp. 118-123.
T. Williams, R. Dennard, R. Kapur, M. Mercer, and W. Maly, “IDDQ Test: Sensitivity Analysis of Scaling,” International Test Conference, 1996, pp. 786-792.
A.E. Gattiker and W. Maly, “Current Signatures,” IEEE VLSI Test Symp., 1996, pp. 112-117.
C. Thibeault, “On the Comparison of1IDDQ and IDDQ Testing,” IEEE VLSI Test Symp., 1999, pp. 143-150.
C. Thibeault, “Increasing Current Testing Resolution,” IEEE Int'l Symp. On Defect and Fault Tolerance, 1998, pp. 126-134.
P. Nigh, W. Needham, K. Butler, P. Maxwell, and R. Aitken, “An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, IDDQ, and Delay-Fault Testing,” IEEE VLSI Test Symp., 1997, pp. 459-463.
A.H. Bowker and G.L. Lieberman, Engineering Statistics, 2nd edn., Prentice-Hall, New Jersey, 1972.
S.M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, McGraw-Hill, New York, 1996.
W. Maly and S.W. Director (Eds.), Statistical Approach to VLSI, North Holland, Amsterdam, 1994.
N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2nd edn., Addison-Wesley, Reading (MA), 1993.
A.E. Gattiker and W. Maly, “Current Signatures: Application,” IEEE Int'l Test Conf., 1997, pp. 156-165.
J.G. Proakis, Digital Communications, 3rd edn., McGraw-Hill, New York, 1983.
IEEE Test Technology Technical Committee, “Sematech Experiment Roundtable,” IEEE Design & Test of Computers, Vol. 15, No. 1, p. 89, Jan.-March 1998.
F. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinatorial Benchmark Circuits and a Target Translator in FORTRAN,” Proc. ISCAS, 1985, pp. 695-698.
D.J. Burns, “Locating High Resistance Shorts in CMOS Circuits by Analyzing Supply Current MeasurementVectors,” Proc. ISTFA, Nov. 1989.
P. Nigh, D. Forlenza, and F. Motika, “Application and Analysis of IDDQ Diagnostic Software,” IEEE Int'l Test Conf, 1997, pp. 319-327.
C. Thibeault, “An Histogram-Based Procedure for Current Testing of Active Defects,” IEEE Int'l Test Conf., 1999, pp. 714-723.
D. Josephson, M. Storey, and D. Dixon, “Microprocessor IDDQ Testing: A Case Study,” IEEE Design & Test of Computers, Vol. 12, No. 2, pp. 42-52, Summer 1995.
C. Thibeault, “On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis,” IEEE Int. Symp. on Defect and Fault Tolerance, 1998, pp. 202-210.
C. Thibeault, “A Novel Probabilistic Approach for IC Diagnosis Based on Differential Quiescent Current Signatures,” IEEE VLSI Test Symp., 1997, pp. 80-85.
C. Thibeault and L. Boisvert, “Diagnosis Method Based on 1IDDQ Probabilistic Signatures: Experimental Results,” IEEE Int'l Test Conf., 1998, pp. 1019-1026.
A.E. Gattiker andW. Maly, “Towards Understanding Iddq-Only Fails,” IEEE Int'l Test Conf., 1998, pp. 174-183.
R. Rodriguez-Montanes, E.M.J.G. Bruls, and J. Figueras, “Bridging Defects Resistance Measurements in a CMOS Process,” IEEE Int'l Test Conf., 1992, pp. 892-899.
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Thibeault, C. Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results. Journal of Electronic Testing 16, 339–353 (2000). https://doi.org/10.1023/A:1008365918776
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DOI: https://doi.org/10.1023/A:1008365918776