Abstract
This paper describes three new march tests for multiport memories. A read (or write) port in such a memory consists of an n-bit address register, an n-to-2n-bit decoder (with column multiplexers for the column addresses) and drivers, and a K-bit data register. This approach gives comprehensive fault coverage for both array and multiport decoder coupling faults. It lends itself to a useful BIST implementation with a modest area overhead that tests these faults and achieves low test application time.
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Chakraborty, K., Mazumder, P. New March Tests for Multiport RAM Devices. Journal of Electronic Testing 16, 389–395 (2000). https://doi.org/10.1023/A:1008374220593
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DOI: https://doi.org/10.1023/A:1008374220593