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Testing the Local Interconnect Resources of SRAM-Based FPGA's

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Abstract

This paper addresses the problem of testing the configurable modules used in the local interconnect of SRAM-based FPGAs. First, it is demonstrated that a n address bit Configurable Interface Multiplexer requires N = 2n test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable Interface Modules with n address bits is analyzed and it is proven that the set of CIMs can be tested in parallel making the number of required test configurations equal to N = 2n. Third, it is shown that the complete circuit i.e. a m × m array of sets of k Configurable Interface Multiplexers with n address bits can be tested with only N = 2n test configurations using the XOR tree and shift register structures.

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Renovell, M., Portal, J., Figueras, J. et al. Testing the Local Interconnect Resources of SRAM-Based FPGA's. Journal of Electronic Testing 16, 513–520 (2000). https://doi.org/10.1023/A:1008376917755

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