Skip to main content
SpringerLink
Log in

A Buffer-Oriented Methodology for Microarchitecture Validation

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

We propose a methodology for validating microarchitecture specifications. We view microarchitecture features as specific operations on entries of various buffers in the processor. Our validation approach is to determine the functionality of a buffer type, model its operations at the microarchitecture level using abstract finite state machine (FSM) models, and rigorously generate instruction sequences that systematically exercise the model of each instance of that buffer type. A high-level test sequence is derived based on the abstract FSM model using FSM testing techniques, and then translated to a test program that exercises the functionality of each buffer entry. This methodology is applied to the microarchitecture specifications of the PowerPC 604. The effectiveness of the sequences generated using our methodology is compared with that of some real and randomly-generated programs. Simulation results show that all targeted FSM transitions are covered by our sequences with at least 1000 × and 3 × fewer instructions than real and randomly-generated programs, respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. B. Black and J.P. Shen, “Calibration of Microprocessor Performance Models,” IEEE Computer, Vol. 31, No. 5, pp. 59–65, May 1998.

    Google Scholar 

  2. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, Piscataway, NJ, 1991.

    Google Scholar 

  3. R.E. Bryant, “Graph Based Algorithms for Boolean Function Manipulation,” IEEE Transactions on Computers, Vol. C-35, No. 8, pp. 677–691, Aug. 1986.

    Google Scholar 

  4. R.E. Bryant, D.L. Beatty, and C.J.H. Seger, “Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation,” Proc. of Design Automation Conference (DAC), June 1991, pp. 397–402.

  5. M.C. McFarland, “Formal Verification of Sequential Hardware: A Tutorial,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 5, pp. 633–654, May 1993.

    Google Scholar 

  6. K.L. McMillan, Symbolic Model Checking, Kluwer Academic Publishers, 1993.

  7. M. Yoeli, Formal Verification of Hardware Design, IEEE Computer Society Press, Los Alamitos, CA, 1990.

    Google Scholar 

  8. J. Burch and D. Dill, “Automatic Verification of Pipelined Microprocessor Control,” International Conference on Computer Aided Verification, June 1994, pp. 68–80.

  9. K.L. Nelson, A. Jain, and R.E. Bryant, “Formal Verification of a Superscalar Execution Unit,” Proc. of Design Automation Conference (DAC), June 1997, pp. 161–166.

  10. C.L. Berman and L.H. Trevillyan, “Functional Comparison of Logic Designs for VLSI Circuits,” Proc. of International Conference on Computer Design (ICCD), Nov. 1989, pp. 456–459.

  11. D.L. Beatty and R.E. Bryant, “Formally Verifying a Microprocessor Using a Simulation Methodology,” Proc. of Design Automation Conference, June 1994, pp. 596–602.

  12. D. Geist, M. Farkas, A. Landver, Y. Lichtenstein, S. Ur, and Y. Wolfsthal, “Coverage-Directed Test Generation Using Symbolic Techniques,” Proc. of the International Conference in Formal Methods in Computer-Aided Design, Nov. 1996, pp. 143–158.

  13. R.C. Ho, C.H. Yang, M.A. Horowitz, and D.L. Dill, “Architecture Validation for Processors,” Proc. of the International Symposium on Computer Architecture, June 1995, pp. 404–413.

  14. H. Iwashita, S. Kowatari, T. Nakata, and F. Hirose, “Automatic Test Program Generation for Pipelined Processors,” Proc. of International Conference on Computer-Aided Design, Nov. 1994, pp. 580–583.

  15. D. Moundanos, J.A. Abraham, and Y.V. Hoskote, “Abstraction Techniques for Validation Coverage Analysis and Test Generation,” IEEE Transactions on Computers, Vol. 47, No. 1, pp. 2–14, Jan. 1998.

    Google Scholar 

  16. N. Utamaphethai, R.D. Blanton, and J.P. Shen, “Superscalar Processor Validation at the Microarchitecture Level,” Digest of Papers of the International High Level Design Validation and Test Workshop (HLDVT), Nov. 1997, pp. 202–209.

  17. N. Utamaphethai, R.D. Blanton, and J.P. Shen, “Validation of Speculative adn Out-of-Order Execution Microarchitecture,” First International Workshop on Microprocessor Test and Verification, Oct. 1998.

  18. N. Utamaphethai, R.D. Blanton, and J.P. Shen, “Superscalar Processor Validation at the Microarchitecture Level,” Proc. of International Conference on VLSI Design, Jan. 1999, pp. 300–305.

  19. Jr. A.G. Liles and B.E. Willner, “Branch Prediction Mechanism,” IBM Technical Disclosure Bulletin, Vol. 22, No. 7, pp. 3013–3016, Dec. 1979.

    Google Scholar 

  20. J.K.F. Lee and A.J. Smith, “Branch Prediction Strategies and Branch Target Buffer Design,” IEEE Computer, pp. 6–22, Jan. 1984.

  21. R.M. Keller, “Look-Ahead Processors,” Computing Surveys, Vol. 7, No. 4, pp. 177–195, Dec. 1975.

    Google Scholar 

  22. R.M. Tomasulo, “An Efficient Algorithm for Exploiting Multiple Arithmetic Units,” IBM Journal, Vol. 11, No. 1, pp. 25–33, Jan. 1967.

    Google Scholar 

  23. J.E. Smith and A.R. Pleszkun, “Implementation of Precise Interrupts in Pipelined Processors,” Proc. of the International Symposium on Computer Architecture, June 1985, pp. 36–44.

  24. Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, New York, 1978.

    Google Scholar 

  25. S. Naito and M. Tsunoyama, “Fault Detection for Sequential Machines by Transition-Tours,” Proc. of the Interanational Symposium on Fault-Tolerant Computing, June 1981, pp. 238–243.

  26. T.A. Diep, “VMW: A Visualization-based Microarchitecture Workbench,” Ph.D. Thesis, Carnegie Mellon University, Aug. 1995.

  27. A.S. Huang and T.A. Diep, “MW Developer's Guide,” Technical Report, CMuART–95–1, Carnegie Mellon University, Aug. 1995.

  28. A. Aharon, A. Bar-David, B. Dorfman, E. Gofman, M. Leibowitz, and V. Schwartzburd, “Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-Random Test Program Generator,” IBM System Journal, Vol. 30, No. 4, pp. 527–538, 1991.

    Google Scholar 

  29. P. Bose, “Architectural Timing Verification and Test for Superscalar Processors,” Proc. of the International Symposium on Fault-Tolerant Computing, June 1994, pp. 256–265.

  30. P. Bose, “Performance Test Case Generation for Microprocessors,” Proc. of VLSI Test Symposium, Apr. 1998, pp. 54–59.

  31. N. Dohm et al., “Zen and Art of Alpha Verification Microarchitecture Level,” Proc. of International Conference on Computer Design, Oct. 1998, pp. 111–117.

  32. S.T. Mangelsdorf et al., “Functional Verification of the HP PA 8000 Processor,” Hewlett-Packard Journal, pp. 22–31, Aug. 1997.

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, 15213

    Noppanunt Utamaphethai

  2. Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, 15213

    R.D. (Shawn) Blanton

  3. Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, 15213

    John Paul Shen

Authors
  1. Noppanunt Utamaphethai
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. R.D. (Shawn) Blanton
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. John Paul Shen
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Utamaphethai, N., Blanton, R.(. & Shen, J.P. A Buffer-Oriented Methodology for Microarchitecture Validation. Journal of Electronic Testing 16, 49–65 (2000). https://doi.org/10.1023/A:1008384521954

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1008384521954

Search

Navigation