Abstract
We propose a static compaction procedure to reduce the test application time for full and partial scan synchronous sequential circuits. The procedure accepts as input a set of test subsequences. A test subsequence consists of a sequence of primary input vectors, and a vector to be scanned-in before the input sequence is applied. The procedure uses two operations to reduce the test application time. The first operation combines test subsequences. The second operation reduces the lengths of the combined subsequences (the length of a test subsequence is the length of the input sequence included in it). The reductions in test application time of the proposed procedure are demonstrated through experimental results.
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Pomeranz, I., Reddy, S.M. Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. Journal of Electronic Testing 16, 541–552 (2000). https://doi.org/10.1023/A:1008385125818
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DOI: https://doi.org/10.1023/A:1008385125818