Abstract
We give three new algorithms to compute tests for faults in the interconnects of random access memories (RAM) using only read and write operations. Diagnosis of address line faults is the most difficult step. Our Adaptive Diagnosis Algorithm (ADA) considers each address line separately. Single line faults are easy to diagnose, so the objective is to ascertain which address lines are free of faults, thereby pruning impossible multi-line faults. Our Consecutive Diagnosis Algorithm (CDA) uses a more complicated and lengthier test sequence. However, with CDA, interpreting the test results is easier and the diagnostic resolution is superior. Our third algorithm, Adaptive Diagnosis Algorithm with Repair (ADAR), relies upon additional testing after repair in order to diagnose more faults than would otherwise be possible. ADAR has three test stages with two repair stages between them.
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Zhao, J., Meyer, F.J. & Lombardi, F. Adaptive Fault Detection and Diagnosis of RAM Interconnects. Journal of Electronic Testing 15, 157–171 (1999). https://doi.org/10.1023/A:1008396604722
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DOI: https://doi.org/10.1023/A:1008396604722