Verification Simulation Acceleration Using Code-Perturbation

Abstract

We propose a simulation approach that can take a large design and swiftly cover its valid code-level operating states. The approach perturbs the program-control flow during the simulation to dynamically exhaust all branching possibilities in a verification code/program. The heuristic uses the program branching information from preprocessing the test/verification code. Using the branching information the simulation allows automatic run-time forced branching to make possible a full coverage of the instruction space spanned by the verification code/program. The aim is (1) to improve the verification simulation speed and (2) to get higher coverage rate for large core-base designs such as microprocessors or digital-signal-processing (DSP) products. A case study of a 32-bit RISC processor, used in a network system, is conducted. The application code for the processor (MCP, Myrinet control program) is used as a verification program. Despite the deviation from the valid “software-reachable state” of the system due to forced branching, a significant number of hard-to-reach hardware states (that can be reached only through the right mix of codes, often the code segments of an application software) are covered. Using the MCP program over 30% additional coverage is achieved with the proposed approach over ordinary code-based simulation for a fixed verification time. Further, compared to the conventional simulation approach, the proposed heuristic takes about 43% less compute-cycles to achieve same state coverage level.