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Design for Testability Techniques at the Behavioral and Register-Transfer Levels

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Abstract

Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high-level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.

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Authors and Affiliations

  1. Department of ECE, University of California, San Diego, La Jolla, CA, 92093

    Sujit Dey

  2. C&C Research Labs, NEC USA, Princeton, NJ, 08540

    Anand Raghunathan

  3. Siemens Microelectronics Inc, San Jose, CA

    Kenneth D. Wagner

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  1. Sujit Dey
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  2. Anand Raghunathan
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  3. Kenneth D. Wagner
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Dey, S., Raghunathan, A. & Wagner, K.D. Design for Testability Techniques at the Behavioral and Register-Transfer Levels. Journal of Electronic Testing 13, 79–91 (1998). https://doi.org/10.1023/A:1008397519162

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