Abstract
We define a new liveness condition for asynchronous circuits. Although finitary (finite-execution) descriptions are not powerful enough to express general liveness properties, those liveness properties needed in practice appear to be related in a unique manner to finitary descriptions. Our liveness condition exploits this observation and is defined directly on finitary descriptions, in two forms: one on finite trace structures and the other on finite automata. We prove the equivalence of these two forms. We also introduce a safety condition and derive theorems for the modular and hierarchical verification theorems of both safety and liveness. Finally, we give an algorithm for verifying our liveness condition.
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Negulescu, R., Brzozowski, J. Relative Liveness: From Intuition to Automated Verification. Formal Methods in System Design 12, 73–115 (1998). https://doi.org/10.1023/A:1008602014766
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DOI: https://doi.org/10.1023/A:1008602014766