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Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets

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Abstract

This paper approaches the problem of synthesising an asynchronous control circuit for a stage of the Sproull Counterflow pipeline processor (CFPP) as an exercise in exploiting formal techniques available for Petri nets. We first synthesise a Petri net model of the CFPP stage control from its original “five-state-five-event” description due to Charles Molnar. Secondly, we implement that model in asynchronous circuits, using two-phase and four-phase components. The latter stage involves synthesising circuits with arbitration elements from behavioural descriptions with internal conflicts. This exercise appears to be quite instructive in the sense that it helps to estimate the scope and power of formal methods and today's automatic tools in assisting the process of asynchronous design.

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  1. Department of Computing Science, University of Newcastle upon Tyne, NE1 7RU, England.

    Alexandre Yakovlev

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  1. Alexandre Yakovlev
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Yakovlev, A. Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets. Formal Methods in System Design 12, 39–71 (1998). https://doi.org/10.1023/A:1008649930696

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