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APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations

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Abstract

Dataflow has proven to be an attractive computational model for graphical DSP design environments that support the automatic conversion of hierarchical signal flow diagrams into implementations on programmable processors. The synchronous dataflow (SDF) model is particularly well-suited to dataflow-based graphical programming because its restricted semantics offer strong formal properties and significant compile-time predictability, while capturing the behavior of a large class of important signal processing applications. When synthesizing software for embedded signal processing applications, critical constraints arise due to the limited amounts of memory. In this paper, we propose a solution to the problem of jointly optimizing the code and data size when converting SDF programs into software implementations.

We consider two approaches. The first is a customization to acyclic graphs of a bottom-up technique, called pairwise grouping of adjacent nodes (PGAN), that was proposed earlier for general SDF graphs. We show that our customization to acyclic graphs significantly reduces the complexity of the general PGAN algorithm, and we present a formal study of our modified PGAN technique that rigorously establishes its optimality for a certain class of applications. The second approach that we consider is a top-down technique, based on a generalized minimum-cut operation, that was introduced recently in [14]. We present the results of an extensive experimental investigation on the performance of our modified PGAN technique and the top-down approach and on the trade-offs between them. Based on these results, we conclude that these two techniques complement each other, and thus, they should both be incorporated into SDF-based software implementation environments in which the minimization of memory requirements is important. We have implemented these algorithms in the Ptolemy software environment [5] at UC Berkeley.

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Authors and Affiliations

  1. Semiconductor Research Laboratory, Hitachi America, Ltd., 201 East Tasman Drive, San Jose, California, 95134, USA

    Shuvra S. Bhattacharyya

  2. Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley, California, 94720, USA

    Praveen K. Murthy & Edward A. Lee

Authors
  1. Shuvra S. Bhattacharyya
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  2. Praveen K. Murthy
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  3. Edward A. Lee
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Bhattacharyya, S.S., Murthy, P.K. & Lee, E.A. APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations. Design Automation for Embedded Systems 2, 33–60 (1997). https://doi.org/10.1023/A:1008806425898

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