Abstract
In this paper, we address the issues of designing lowpower VLSI implementation of the Code DivisionMultiple Access (CDMA) receiver. Among all the digitalfunctional blocks of a CDMA receiver, the RAKEreceiver and the Viterbi decoder are the mostcomputational intensive and hence consume most of thepower. In this work, we propose new VLSI architecturesfor these two functional blocks which consumesignificantly lower power. In particular, were-organize the structure of the pilot-aided RAKEdemodulator to reduce the operational frequency of thearithmetic components and we propose a newAdd-Compare-Select (ACS) architecture for the Viterbidecoder which can reduce the complexity of thecomputation. Also a novel pre-computationalarchitecture is proposed to further reduce the powerconsumption of the ACS unit. Experimental results showsignificant reduction in power consumption.
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Tsui, Cy., Cheng, R.SK. & Ling, C. Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications. Wireless Personal Communications 14, 49–64 (2000). https://doi.org/10.1023/A:1008961028130
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DOI: https://doi.org/10.1023/A:1008961028130