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Minimization of Data Address Computation Overhead in DSP Programs

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Abstract

Modern digital signal processors (DSPs) provide dedicated address generation units (AGUs) which support data memory access by indirect addressing with automatic address modification in parallel to other machine operations. There is no address computation overhead if the next address is within the auto-modify range. Typically, optimization of data memory layout and address register assignment allows to reduce both execution time and code size of DSP programs. In this paper, we present an optimization technique for integrated data memory layout generation and address register assignment. We use a generic AGU model which captures important addressing capabilities of DSPs such as linear addressing, modulo addressing, auto-modifying, and indexing within a given auto-modify range. Experimental results demonstrate that the proposed technique significantly outperforms existing optimization strategies.

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References

  1. V. Zivojnovic, J. M. Velarde, C. Schläger, and H. Meyr. DSPstone: a DSP-oriented benchmarking methodology. In Proc. 5th Int. Conf. on Signal Processing Applications & Technology, volume 1, pp. 715-720, Dallas, October 1994.

    Google Scholar 

  2. P. Marwedel and G. Goossens, Eds. Code Generation for Embedded Processors. Kluwer Academic Publishers, 1995.

  3. G. Goossens, J. V. Praet, D. Lanneer, W. Geurts, A. Kifli, C. Liem, and P. G. Paulin. Embedded software in real-time signal processing systems: design technologies. Proc. IEEE, 85(3): 436-454, March 1997.

    Article  Google Scholar 

  4. R. Leupers. Retargetable Code Generation for Digital Signal Processors. Kluwer Academic Publishers, 1997.

  5. C. Liem. Retargetable Compilers for Embedded Core Processors. Kluwer Academic Publishers, 1997.

  6. D. H. Bartley. Optimizing stack frame accesses for processors with restricted addressing modes. Software-Practice and Experience, 22(2): 101-110, February 1992.

    Google Scholar 

  7. S. Liao, S. Devadas, K. Keutzer, S. Tjiang, and A. Wang. Storage assignment to decrease code size. ACM Trans. on Programming Languages and Systems, 18(3): 235-253, May 1996.

    Article  Google Scholar 

  8. R. Leupers and P. Marwedel. Algorithms for address assignment in DSP code generation. In Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 109-112, San Jose, November 1996.

  9. N. Sugino, H. Myiazaki, S. Iimuro, and A. Nishihara. Improved code optimization method utilizing memory addressing and its application to compilers. In Proc. IEEE Int. Symp. on Circuits and Systems, volume 2, pp. 249-252, Atlanta, May 1996.

    Google Scholar 

  10. B. Wess and M. Gotschlich. Constructing memory layouts for address generation units supporting offset 2 access. In Proc. IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, volume 1, pp. 683-686, Munich, April 1997.

    Google Scholar 

  11. N. Kogure, N. Sugino, and A. Nishihara. Memory address allocation method for a DSP with ±2 update operations in indirect addressing. In Proc. Europ. Conf. on Circuit Theory and Design, Budapest, September 1997.

  12. A. Sudarsanam, S. Liao, and S. Devadas. Analysis and evaluation of address arithmetic capabilities in custom DSP architectures. In Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, June 1997.

  13. Analog Devices, Inc. ADSP-2100 Family User's Manual, September 1995.

  14. Motorola, Inc. DSP56000 Digital Signal Processor Family Manual, 1992.

  15. Texas Instruments, Inc. TMS320C5x User's Guide, 1997.

  16. C. H. Papadimitriou. The NP-completeness of the bandwidth minimization problem. Computing, 16: 263-270, 1976.

    Article  MATH  MathSciNet  Google Scholar 

  17. J. B. Saxe. Dynamic-programming algorithms for recognizing small-bandwidth graphs in polynomial time. SIAM J. Alg. Disc. Meth., 1(4): 363-369, December 1980.

    MATH  MathSciNet  Google Scholar 

  18. M. R. Garey, R. L. Graham, D. S. Johnson, and D. E. Knuth. Complexity results for bandwidth minimization. SIAM J. Appl. Math., 34(3): 477-495, May 1978.

    Article  MATH  MathSciNet  Google Scholar 

  19. R. E. Burkard. Quadratic assignment problems. Europ. Journal of Operational Research, 15: 283-289, 1984.

    Article  MATH  MathSciNet  Google Scholar 

  20. R. E. Burkard and F. Rendl. A thermodynamically motivated simulation procedure for combinatorial optimization problems. Europ. Journal of Operational Research, 17: 169-174, 1984.

    Article  MATH  Google Scholar 

  21. J. Skorin-Kapov. Tabu search applied to the quadratic assignment problem. ORSA Journal on Computing, 2(1): 33-45, 1990.

    MATH  Google Scholar 

  22. S. Kirkpatrick, Jr., C. D. Gelatt, and M. P. Vecchi. Optimization by simulated annealing. Science, 220(4598): 671-680, May 1983.

    MathSciNet  Google Scholar 

  23. P. C. Gilmore. Optimal and suboptimal algorithms for the quadratic assignment problem. J. SIAM, 10: 305-313, 1962.

    MATH  MathSciNet  Google Scholar 

  24. E. L. Lawler. The quadratic assignment problem. Management Science, 9: 586-599, 1963.

    Article  MATH  MathSciNet  Google Scholar 

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  1. Institut F. Nachrichtentechnik u. Hochfrequenztechnik, Vienna University of Technology, Austria

    Bernhard Wess

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  1. Bernhard Wess
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Wess, B. Minimization of Data Address Computation Overhead in DSP Programs. Design Automation for Embedded Systems 4, 167–185 (1999). https://doi.org/10.1023/A:1008961206784

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