Skip to main content
SpringerLink
Log in

Distributed Memory Parallel Architecture Based on Modular Linear Arrays for 2-D Separable Transforms Computation

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

A framework for mapping systematically 2-dimensional (2-D) separable transforms into a parallel architecture consisting of fully pipelined linear array stages is presented. The resulting model architecture is characterized by its generality, high degree of modularity, high throughput, and the exclusive use of distributed memory and control. There is no central shared memory block to facilitate the transposition of intermediate results, as it is commonly the case in row-column image processing architectures. Avoiding shared central memory has positive implications for speed, area, power dissipation and scalability of the architecture. The architecture presented here may be used to realize any separable 2-D transform by only changing the coefficients stored in the processing elements. Pipelined linear arrays for computing the 2-D Discrete Fourier Transform and 2-D separable convolution are presented as examples and their performance is evaluated.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. A. Akansu and R. Haddad, Multiresolution Signal Decomposi-tion, Academic Press, 1992.

  2. K.R. Rao and P. Yip, Discrete Cosine Transform: Algorithms, Advantages, and Applications, Academic Press, 1990.

  3. J.I. Guo, C.M. Liu, and C.W. Jen, "An Novel CORDIC-Based Array Architecture for the Multidimensional Discrete Hartley Transform," IEEE Transactions on Signal Processing, vol. 43, no. 1, 1995, pp. 331–336.

    Article  Google Scholar 

  4. Y.-P. Lee, T.-H. Chen, L.-G. Chen, M.-J. Chen, and C.-W. Ku, "A Cost-Effective Architecture for 8 ×8 Two-Dimensional DCT/IDCT Using Direct Method," IEEE Transactions on Circuits and Systems for Video Technology, vol. 7, no. 3, 1997, pp. 459–467.

    Article  Google Scholar 

  5. V. Bhaskaran and K. Konstantinides, Image and Video Com-pression Standars, Kluwer Academic Publishers, 1995, Boston, MA, USA.

  6. I. Gertner and M. Shamash, "VLSI Architectures for Multidi-mensional Fourier Transform Processing," IEEE Transactions on Computers, vol. C-36, 1987, pp. 1265–1274.

    Article  Google Scholar 

  7. C. Chakrabarti and J. J´aj´a, "VLSI Architectures for Multidimen-sional Transforms," IEEE Transactions on Computers, vol. 40, 1991, pp. 1053–1057.

    Article  Google Scholar 

  8. W. Namgoong, N. Chaddha, and T.H.Y. Meng, "Low-Power Video Encoder/Decoder Using Wavelet/TSVQ With Condi-tional Replenishment," in Proc. Int'l. Conf. on Acoustics, Speech and Signal Processing, IEEE Signal Processing Society, 1996, pp. VI-3241, Atlanta, GA, USA.

  9. H. Lim and E.E. Swartzlander, "Multidimensional Systolic Ar-rays for Multidimensional DFTs," in Proc. Int'l. Conf. on Acous-tics, Speech and Signal Processing, IEEE Signal Processing Society, 1996, pp. VI-3277, Atlanta, GA, USA.

  10. C.-L. Wang and Y.-T. Chang, "Highly Parallel VLSI Architec-tures for the 2-D DCTand IDCT Computations," in IEEE Region 10's Ninth Annual Int'l. Conference, 1994, pp. 295–299.

  11. A.L. Fisher and H.T. Kung, "Synchronizing Large Systolic Arrays," in Proc. 10th. Annual Int'l. Symposium on Computer Ar-chitecture, 1983, pp. 54–58.

  12. P. Lee and Z. Kedem, "Synthesizing Linear Array Algorithms from Nested for Loop Algorithms," IEEE Transactions on Computers, vol. 37, no. 12, 1988, pp. 1578–1598.

    Article  MathSciNet  MATH  Google Scholar 

  13. E.E. Swartzlander Jr., VLSI Signal Processing Systems, Kluwer-Academic, 1986.

  14. C.D. Thompson, "Fourier Transforms in VLSI," IEEE Transactions on Computers, vol. C-32, 1983, pp. 1047–1057.

    Article  Google Scholar 

  15. J.A. Beraldin, T. Aboulnasr, and W. Steenaart, "Efficient One-Dimensional Systolic Array Realization of the Discrete Fourier Transform," IEEE Transactions on Circuit and Systems, vol. 36, no. 1, 1989, pp. 95–100.

    Article  Google Scholar 

  16. D.E. Dudgeon and R.M. Mersereau, Multidimensional Digital Signal Processing, Prentice-Hall, 1984.

  17. J.F. Abramatic, F. Germain, and E. Rosencher, "Design of 2-D Recursive Filters with Separable Denominator Transfer Functions," in Proc. IEEE Int't. Conf. Accoustics, Speech and Signal Processing, April 1979, pp. 24–27.

  18. S. Treitel and J.L. Shanks, "The Design of Multistage Separable Planar Filters," IEEE Transactions on Geoscience Electronics, vol. GE-9, no. 1, 1971, pp. 10–27.

    Article  Google Scholar 

  19. J. Fridman, "Parallel Algorithms and Architectures for Discrete Wavelet Transforms," Ph.D. Thesis, Northeastern University, 1996.

  20. A. Jain, Fundamentals of Digital Image Processing, Prentice-Hall, 1989.

  21. G. Golub and C. Van Loan, Matrix Computations, Johns Hopkins University Press, 1989, Baltimore, MD, USA.

    MATH  Google Scholar 

  22. R. Tolimieri, M. An, and C. Lu, Algorithms for Discrete Fourier Transform and Convolution, New York: Springer-Verlag, 1989.

    Book  MATH  Google Scholar 

  23. S.Y. Kung, VLSI Array Processors, Prentice Hall, 1989.

  24. W. Shang and J.A.B. Fortes, "On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays," IEEE Trans. on Parallel and Distributed Systems 203 vol. 3, no. 3, 1992, pp. 350–363.

    Article  Google Scholar 

  25. J. Bu, E.F. Deprettere, and L. Thiele, "Systolic Array Imple-mentation of Nested Loop Programs," in Proc. of IEEE Int'l Conference on Application Specific Array Processors, 1990, pp. 31–42.

  26. S. Rajopadhye, "Synthesizing Systolic Arrays with Control Sig-nals from Recurrence Equations," Distributed Computing, vol. 3, 1988, pp. 88–105.

    Article  Google Scholar 

  27. J. Ullman, Computational Aspects of VLSI, Computer Science Press, 1984, Rockville, MD, USA.

    MATH  Google Scholar 

  28. J. Fridman and E. Manolakos, "On the Synthesis of Regular VLSI Architectures for the 1-D Discrete Wavelet Transform," in Wavelet Applications in Signal and Image Processing II Proceedings, A. Lane and M. Unser (Eds.), SPIE, July 1994, pp. 91–104, San Diego, CA, USA.

  29. J. Fridman and E.S. Manolakos, "Distributed Memory and Con-trol VLSI Architectures for the 1-D Discrete Wavelet Transform," in VLSI Signal Processing VII, J. Rabaey, P. Chau, and J. Eldon (Eds.), IEEE Signal Processing Society, October 1994, pp. 388–397, New York, NY, USA.

  30. J. Fridman and E.S. Manolakos, "1-D Discrete Wavelet Trans-form: Data Dependence Analysis and Synthesis of Distributed Memory and Control Array Architectures," IEEE Transactions on Signal Processing, vol. 45, no. 5, 1997, pp. 1291–1308.

    Article  Google Scholar 

  31. A. Stone and E.S. Manolakos, "DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Archi-tectures," Journal of VLSI Signal Processing Systems, vol. 24, no. 1, 2000, pp. 99–120.

    Article  MATH  Google Scholar 

  32. "DG2VHDL: A Tool to Facilitate the Synthesis of Parallel VLSI Architectures," http://www.cdsp.neu.edu/info/faculty/ manolakos/dg2vhdl root.html.

  33. D.W. Knapp, Behavioral Synthesis. Digital System Design Using the Synopsys Behavioral Compiler, Prentice Hall, 1996, Upper Saddle River, NJ, USA.

    Google Scholar 

  34. A. Stone and E.S. Manolakos, "Using DG2VHDL to Synthe-size an FPGA Implementation of the 1-D Discrete Wavelet Transform," in Proc. of IEEE Signal Processing Systems (SiPS), October 1998, pp. 489–498.

  35. J. Bonk, A. Stone, and E.S. Manolakos, "Synthesis of Array Architectures of Block Matching Motion Estimation: Design Exploration Using the Tool DG2VHDL," in Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, IEEE Press, 1999, pp. 1925–1928, Phoenix, AZ USA.

  36. R. Anamalai, "Design and Synthesis of Maximum Throughout Parallel Array Architectures for Real-Time Image Transforms, MS Thesis, ECE Dept. Northeastern University, 1998.

Download references

Author information

Authors and Affiliations

  1. Analog Devices, Norwood, MA, USA

    José Fridman

  2. Communications and Digital Signal Processing (CDSP), Center for Research and Graduate Studies, Electrical and Computer Engineering Department, Northeastern University, 442 Dana Research Build., Boston, MA, 02115, USA

    Elias S. Manolakos

Authors
  1. José Fridman
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Elias S. Manolakos
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Fridman, J., Manolakos, E.S. Distributed Memory Parallel Architecture Based on Modular Linear Arrays for 2-D Separable Transforms Computation. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 28, 187–203 (2001). https://doi.org/10.1023/A:1011113507906

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1011113507906

Search

Navigation