Abstract
Dynamic hardware reconfiguration based on run-time system specialization is viable with FPGAs. The research challenge for formal verification is to help ensure the correctness of dynamically generated hardware. In this paper, the approach is to verify a specialization synthesis algorithm used to reconfigure FPGA designs at run-time. The verification approach is based on a deep embedding of a language for netlist and the relational hardware modeling style.
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Susanto, K.W., Melham, T. Formally Analyzed Dynamic Synthesis of Hardware. The Journal of Supercomputing 19, 7–22 (2001). https://doi.org/10.1023/A:1011132326153
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DOI: https://doi.org/10.1023/A:1011132326153