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Fault Models and Test Generation for OpAmp Circuits—The FFM

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Abstract

The analog VLSI technology processes are reaching the matureness, nevertheless, there is a big constraint, regarding their use on complex electronic products: “the test”. The “Design for Testability” paradigm was developed to permit the test plan implementation early in the design cycle. However to succeed onto this strategy, the fault simulation should be carried out in order to evaluate appropriate test patterns, fault grade and so forth. Consequently adequate fault models must be established. Due to the lack of fault models, suitable to fault simulation on OpAmps, we propose in this work a methodology for Functional Fault Modeling-FFM, and some methods for test generation. A fault dictionary for OpAmps is built and a procedure for compact test vector construction is proposed. The results have shown that high level OpAmp requirements, as slew-rate, common mode rejection ration etc., can be checked by this approach with good compromise between the fault modeling problem, the analog nature of the circuit and the circuit complexity by itself.

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Authors and Affiliations

  1. Brazilian Navy Research Institute, R. Ipiru, 2, Rio de Janeiro, Brazil

    José Vicente Calvano

  2. Federal University of Rio de Janeiro/COPPE, Av. Brigadeiro Trompowski, s/n, Brazil

    Antônio Carneiro de Mesquita Filho & Vladimir Castro Alves

  3. Federal University of Rio Grande do Sul/DELET, Av. Oswaldo Aranha, 103, Porto Alegre, Brazil

    Marcelo Soares Lubaszewski

Authors
  1. José Vicente Calvano
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  2. Antônio Carneiro de Mesquita Filho
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  3. Vladimir Castro Alves
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  4. Marcelo Soares Lubaszewski
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Calvano, J.V., de Mesquita Filho, A.C., Alves, V.C. et al. Fault Models and Test Generation for OpAmp Circuits—The FFM. Journal of Electronic Testing 17, 121–138 (2001). https://doi.org/10.1023/A:1011169626409

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