Abstract
Many VLSI architectures for computing the discrete wavelet transform (DWT) were presented, but the parallel input data sequence and the programmability of the 2-D DWT were rarely mentioned. In this paper, we present a parallel-processing VLSI architecture to compute the programmable 2-D DWT, including various wavelet filter lengths and various wavelet transform levels. The proposed architecture is very regular and easy for extension. To eliminate high frequency components, the pixel values outside the boundary of the image are mirror-extended as the symmetric wavelet transform (SWT) and the mirror-extension is realized via the routing network. Owing to the property of the parallel processing, we adopt the row-based recursive pyramid algorithm (RPA), similar to 1-D RPA, as the data scheduling. This design has been implemented and fabricated in a 0.35 μm 1P4M CMOS technology and the working frequency is 50 MHz. The chip size is about 5200 μm × 2500 μm. For a 256 × 256 image, the chip can perform 30 frames per second with the filter length varying from 2 to 20 and with various levels. The proposed architecture is suitable for real-time applications such as JPEG 2000.
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References
G. Knowles, "VLSI Architecture for the Discrete Wavelet Trans-form," Electronics Letters, vol. 26, 1990, pp. 1184–1185.
K.K. Parhi and T. Nishitani, "VLSI Architecture for Discrete Wavelet Transforms," IEEE Trans. on VLSI Systems, vol. 1, no. 2, 1993, pp. 191–202.
R.M. Owens and M. Vishwanath, "A Very Efficient Storage Structure for DWT and IDWT Filters," Journal of VLSI Signal Processing, vol. 19, 1998, pp. 215–225.
M. Vishwanath, "The Recursive Pyramid Algorithm for the Dis-crete Wevelet Transform," IEEE Trans. on Signal Processing,vol 42, no. 3, 1994, pp. 673–676.
C. Yu and S.J. Chen, "Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transforms," in IEEE International Symposium on Consumer Electronics, Oct. 1998.
M. Vishwanath, R.M. Owens, and M.J. Irwin, "VLSI Archi-tectures for the Discrete Wavelet Transform," IEEE Trans. on Circuits and Systems-II, vol. 42, no. 5, 1995, pp. 305–316.
C. Chakrabarti and M. Vishwanath, "Efficient Realizations of the Discrete and Continuous Wavelet Transforms: From Single Chip Implementation to Mappings on SIMD Array Computers," IEEE Transactions on Signal Processing, vol. 43, no. 3, 1995, pp. 759–771.
J.C. Limqueco and M.A. Bayoumi, "VLSI Architecture for Sep-arable 2-D Discrete Wavelet Transform," Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 18, 1998, pp. 125–140.
J. Fridman and E.S. Manolakos, "Discrete Wavelet Trans-form: Data Dependence Analysis and Synthesis of Distributed Memory and Control Array Architectures," IEEE Transactions on Signal Processing, vol. 45, no. 5, 1997, pp. 1291–1308.
A. Grzeszczak, M.K. Mandal, S. Panchanathan, and T. Yeap, "VLSI Implementation of Discrete Wavelet Transform," IEEE Transactions on VLSI Systems, vol. 4, no. 4, 1996, pp. 421–433.
M. Antonini, M. Barlaud, P. Mathieu, and I. Daubechies, "Image Coding using Wavelet Transform," IEEE Transactions on Image Processing, vol. 1, no. 2, 1992, pp. 205–220.
ISO/IEC JTC 1/SC 29/WGI, JPEG 2000, Part I Final Committee Draft Version 1.0, Apr. 2000.
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Chen, CY., Yang, ZL., Wang, TC. et al. A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 28, 151–163 (2001). https://doi.org/10.1023/A:1011180506997
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DOI: https://doi.org/10.1023/A:1011180506997