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SIVA: A System for Coverage-Directed State Space Search

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Abstract

We introduce SImulation Verification with Augmentation (SIVA), a tool for coverage-directed state space search on digital hardware designs. SIVA tightly integrates simulation with symbolic techniques for efficient state space search. Specifically, the core algorithm uses a combination of ATPG and BDDs to generate “directed” input vectors, i.e., inputs which cover behavior not excited by simulation. We also present approaches to automatically generate “lighthouses” that guide the search towards hard-to-reach coverage goals. Experiments demonstrate that our approach is capable of achieving significantly greater coverage than either simulation or symbolic techniques in isolation.

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References

  1. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital System Testing and Testable Design, IEEE Press, 1990.

  2. U. Berkeley, www.cad.eecs.berkeley.edu/~vis.

  3. R. Bryant, “Graph-based Algorithms for Boolean Function Manipulation,” IEEE Transactions on Computers, vol. C-35, pp. 677-691, August 1986.

  4. J. Burch and V. Singhal, “Tight Integration of Combinational Verification Methods,” in Proc. Intl. Conf. on Computer-Aided Design, 1998, pp. 570-576.

  5. H. Cho, G. Hatchel, E. Macii, M. Poncino, and F. Somenzi, “A State Space Decomposition Algorithm for Approximate FSM Traversal Based on Circuit Structural Analysis,” Technical Report, ECE/VLSI, University of Colorado at Boulder, 1993.

  6. S. Devadas, A. Ghosh, and K. Keutzer, “An Observability-Based Code Coverage Metric for Functional Simulation,” in Proc. Intl. Conf. on Computer-Aided Design, 1996, pp. 418-425.

  7. D.L. Dill, “Embedded Tutorial: What's between Simulation and Formal Verification?,” in Proc. of the Design Automation Conf., San Francisco, CA, 1998, pp. 328-329.

  8. A. El-Maleh, T. Marchok, J. Rajski, and W. Maly, “Behavior and Testability Preservation Under the Retiming Transformation,” vol. 16, pp. 528-543, 1997.

    Google Scholar 

  9. E.A. Emerson, “Temporal and Modal Logic,” in Vol. B: Handbook of Theoretical Computer Science, Formal Models and Semantics, J. van Leeuwen (Ed.), Elsevier Science, 1990, pp. 996-1072.

  10. R.K. Brayton et al., “VIS: A System for Verification and Synthesis,” in Proc. of the Computer Aided Verification Conf., 1996, pp. 428-432.

  11. D. Geist and I. Beer, “Efficient Model Checking by Automated Ordering of Transition Relation Partitions,” in Computer Aided Verification, 1994. Lecture Notes in Computer Science, vol. 818, pp. 52-71.

  12. D. Geist, M. Farkas, A. Landver, Y. Lichtenstein, S. Ur, and Y. Wolfsthal, 1996, “Coverage Directed Test Generation Using Formal Verification,” in Proc. of the Formal Methods in CAD Conf., 1996, pp. 143-158.

  13. P. Goel, “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits,” IEEE Transactions on Computers, vol. C-31, pp. 215-222, 1981.

    Google Scholar 

  14. S. Govindaraju, D. Dill, A. Hu, and M. Horowitz, “Approximate Reachability with BDDs using Overlapping Projections,” in Proc. of the Design Automation Conf., 1998, pp. 451-456.

  15. R. Ho and M. Horowitz, “Validation Coverage Analysis for Complex Digital Designs,” in Proc. Intl. Conf. on Computer-Aided Design, 1996, pp. 146-151.

  16. R.C. Ho, C.H. Yang, M.A. Horowitz, and D.L. Dill, “Architectural Validation for Processors,” in Proceedings of the International Symposium on Computer Architecture, 1995, pp. 404-413.

  17. Y. Hoskote, D. Moundanos, and J. Abraham, “Automatic Extraction of the Control Flow Machine and Application to Evaluating Coverage of Verification Vectors,” in Proc. Intl. Conf. on Computer Design, Austin, TX, 1995, pp. 532-537.

  18. A. Kuehlmann and F. Krohm, “Equivalence Checking Using Cuts and Heaps,” in Proc. of the Design Automation Conf., 1997, pp. 263-268.

  19. K.L. McMillan, Symbolic Model Checking, Kluwer Academic Publishers, 1993.

  20. D. Moundanos, J. Abraham, and Y. Hoskote, “A Unified Framework for Design Validation and Manufacturing Test,” in Proc. Intl. Test Conf., 1996, pp. 875-884.

  21. R. Mukherjee, J. Jain, K. Takayama, M. Fujita, J.A. Abraham, and D.S. Fussell, “Efficient Combination Verification Using Cuts and Overlapping BDDs,” in Proc. Intl. Workshop on Logic Synthesis, 1997.

  22. K. Ravi, K. McMillan, T. Shiple, and F. Somenzi, “Approximation and Decomposition of Binary Decision Diagrams,” in Proc. of the Design Automation Conf., 1998, pp. 445-450.

  23. K. Ravi and F. Somenzi, “High Density Reachability Analysis,” in Proc. Intl. Conf. on Computer-Aided Design, Santa Clara, CA, 1995, pp. 154-158.

  24. E.M. Sentovich, K.J. Singh, C. Moon, H. Savoj, R.K. Brayton, and A.L. Sangiovanni-Vincentelli, “Sequential Circuit Design Using Synthesis and Optimization,” in Proc. Intl. Conf. on Computer Design, 1992, pp. 328-333.

  25. J. Silva and K. Sakallah, “GRASP—A New Search Algorithm For Satisfiability,” in Proc. Intl. Conf. on Computer-Aided Design. Santa Clara, CA, 1996, pp. 220-227.

  26. P. Stephan, R.K. Brayton, and A.L. Sangiovanni-Vincentelli, “Combination Test Generation using Satisfiability,” IEEE Trans. CAD, vol. 15, pp. 1167-1176, 1996.

    Google Scholar 

  27. C.H. Yang and D.L. Dill, “Validation with Guided Search of the State Space,” in Proc. of the Design Automation Conf., 1998, pp. 599-604.

  28. J. Yuan, J. Shen, J. Abraham, and A. Aziz, “On Combining Formal and Informal Verification,” in Proc. of the Computer Aided Verification Conf., 1997, pp. 376-387.

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Ganai, M., Yalagandula, P., Aziz, A. et al. SIVA: A System for Coverage-Directed State Space Search. Journal of Electronic Testing 17, 11–27 (2001). https://doi.org/10.1023/A:1011189608077

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