Skip to main content
SpringerLink
Log in

RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Functional test has long been viewed as unfitted for high-quality production test. The purpose of this paper is to propose a RTL-based test generation methodology which can rewardingly be used both for design validation and to enhance the test effectiveness of classic, gate-level test generation. The proposed methodology leads to high Defects Coverage (DC) and to relatively short test sequences, thus allowing low-energy operation in test mode. The test effectiveness, regarding DC, is shown to be weakly dependent on the structural implementation of the behavioral description. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and the CMUDSP and Torch ITC'99 benchmark circuits.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. T.R. Alcaide, “Modelado de Fallos y Estimación de los Processos de Validación Funcional de Circuits Digitales Descritos en VHDL Sintetizable,” Ph.D. Thesis, Escuela Téc. Sup. Ing. Industriales, U.P. Madrid, 1996.

    Google Scholar 

  2. D. Barclay and J. Armstrong, “A Heuristic Chip-Level Test Generation Algorithm,” in Proc. of the 23rd Design Automation Conference, 1986, pp. 257-262.

  3. L. Bening and H. Foster, Principles of Verifiable RTL Design, Kluwer Academic Publishers, 2000.

  4. V. Chickermane et al., “Addressing Design for Testability at the Architectural Level,” IEEE Trans. on CAD of Int. Circs. and Syst., Vol. 13,No. 7, 1994.

  5. Chung-Hsing and D.G. Saab, “A Novel Behavioral Testability Measure,” IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 12,No. 12, December 1993.

  6. CMUDSP benchmark (I-99-5, ITC 99 5]), http://www.ece.cmu.edu/~lowpower/benchmarks.html

  7. S. Davidson, “ITC'99 Benchmark Circuits—Preliminary Results, Panel 6 session,” in Proc. ITC, 1999, pp. 1126-1130.

  8. Dworak, M.R. Grimaila, S. Lee, L.C. Wang, and M.R. Mercer, “Modeling the Probability of Defect Excitation for a Commercial IC with Implications for Stuck-at-Fault-based ATPG Strategies,” in Proc. Int. Test Conf. (ITC), 1999, pp. 1031-1037.

  9. F. Ferrandi, F. Fummi, and D. Sciuto, “Implicit Test Generation for Behavioral VHDL Models,” in Proc. Int. Test Conf. (ITC), 1998, pp. 587-596.

  10. M.H. Gentil, D. Crestani, A.E. Rhalibi, and C. Durant, “A New Testability Measure: Description and Evaluation,” in IEEE VLSI Test Symp. (VTS), 1994, pp. 421-426.

  11. S. Ghosh and T.J. Chakraborty, “On Behavioral Fault Modeling for Digital Designs,” Journal on Electronic Testing: Theory and Applications, Vol. 2, pp. 135-151, 1991.

    Google Scholar 

  12. X. Gu, K. Kuchcinski, and Z. Peng, “Testability Analysis and Improvement from VHDL Behavioral Specifications,” in Proc. EuroDAC, 1994, pp. 644-649.

  13. G.A. Hayek and C. Robach, “From Specification Validation to Hardware Testing: A Unified Method,” in Proc. Int. Test Conf. (ITC), 1996.

  14. R.J. Hayne and B.W. Johnson, “Behavioral Fault Modeling in a VHDL Synthesis Environment,” in Proc. Int. Test Conf. (ITC), 1999, pp. 333-340.

  15. Y. Levendel and P. Menon, “Test Generation Algorithms for Computer Hardware Description Languages,” IEEE Transactions on Computers, Vol. C-31-7, pp. 577-588, 1982.

    Google Scholar 

  16. T. Lin and S.Y. Su, The S-algorithm: A Promissing Solution for Systematic Functional Test Generation,” IEEE Trans. on CAD, Vol. CAD-4, pp. 250-263, July 1985.

  17. M.A. Iyer, “High Time for High-Level ATPG, Panel 1 session,” in Proc. ITC, 1999, pp. 1113-1119.

  18. P.C. Maxwell and R.C. Aitken, “Test Sets and Reject Rates: All Fault Coverages Are Not Created Equal,” in IEEE Design & Test of Comp., Vol. 10, pp. 42-51, Sept. 1993.

    Google Scholar 

  19. C. Papachristou and J. Carletta, “Test Synthesis in the Behavioral Domain,” in Proc. Int. Test Conference (ITC), 1995, pp. 693-702.

  20. M.B. Santos, F.M. Gonçalves, I.C. Teixeira, and J.P. Teixeira, “Defect-Oriented Verilog Fault Simulation of SoC Macros Using a Stratified Fault Sampling Technique,” in Proc. of the IEEE VLSI Test Symp. (VTS), 1999, pp. 326-332.

  21. M.B. Santos and J.P. Teixeira, “Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL,” in Proc. of the Design Autom. and Test in Europe (DATE) Conf., 1999, pp. 549-553.

  22. S. Sengupta, S. Kundu, S. Chakravarty, P. Parvathala, R. Galivanche, G. Kosonocky, M. Rodgers, and T.M. Mak, “Defect-Based Test: A Key Enabler for Success Migration to Structural Test,” Intel Technology Journal, Q1'99, available at http://www.developer.intel.com/ITJ, 1999.

  23. J.P. Shen, W. Maly, and F.J. Ferguson, “Inductive Fault Analysis of MOS Integrated Circuits,” IEEE Design and Test of Computers, Vol. 2,No. 6, pp. 13-26, December 1985.

    Google Scholar 

  24. J.J.T. Sousa, F.M. Gonçalves, J.P. Teixeira, C. Marzocca, F. Corsi, and T.W. Williams, “Defect Level Evaluation in an IC Design Environment,” IEEE Trans. on CAD, Vol. 15,No. 10, pp. 1286-1293, 1996.

    Google Scholar 

  25. K. Thearling and J. Abraham, “An Easily Functional Level Testability Measure,” in IEEE Int. Test Conference (ITC), 1989, pp. 381-390.

  26. Y. Le Traon and C. Robach, “From Hardware to Software Testability,” in Proc Int. Test Conference (ITC), 1995, pp. 710-719.

  27. TORCH benchmark (I-99-4, ITC 99 5]), http://www-flash.stanford.edu:80/torch/torchspec/

  28. M. Vahid and A. Orailoglu, “Testability Metrics for Synthesis of Self-Testable Designs and Effective Test Plans,” in Proc. IEEE VLSI Test Symp. (VTS), 1995, pp. 170-175.

  29. J.R. Wallack and R. Dandapani, “Coverage Metrics for Functional Tests,” in Proc. IEEE VLSI Test Symp. (VTS), 1994, pp. 176-181.

  30. L.C. Wang, R. Mercer, and T.W. Williams, “On the Decline of Testing Efficiency as Fault Coverage Approaches 100%,” in Proc. IEEE VLSI Test Symp. (VTS), 1995, pp. 74-83.

  31. P.C. Ward and J.R. Armstrong, “Behavioral Fault Simulation in VHDL,” in Proc. 27th. ACM/IEEE Design Automation Conf. (DAC), 1990, pp. 587-593.

  32. Y. Zorian, E. van Marinissen, and S. Dye, “Testing Embedded-Core Based System Chips,” in Proc. Int. Test Conf. (ITC), 1998, pp. 130-143.

Download references

Author information

Authors and Affiliations

  1. Instituto Superior Técnico (IST), INESC.id, R. Alves Redol, 9, 3°, 1000-029, Lisboa, Portugal

    M.B. Santos, F.M. Gonçalves, I.C. Teixeira & J.P. Teixeira

Authors
  1. M.B. Santos
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. F.M. Gonçalves
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. I.C. Teixeira
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. J.P. Teixeira
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Santos, M., Gonçalves, F., Teixeira, I. et al. RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems. Journal of Electronic Testing 17, 311–319 (2001). https://doi.org/10.1023/A:1012223614418

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1012223614418

Search

Navigation