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Application of Deterministic Logic BIST on Industrial Circuits

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Abstract

We present the application of a deterministic logic BIST scheme based on bit-flipping on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5–15%. It is demonstrated that a trade-off is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.

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References

  1. S.B. Akers, “On the Use of Linear Sums in Exhaustive Testing,” in Proceedings International Symposium on Fault-Tolerant Computing, IEEE, 1985, pp. 148-153.

  2. P.H. Bardell, “Design Considerations for Parallel Pseudorandom Pattern Generators,” Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 1,No. 1, pp. 73-87, 1990.

    Google Scholar 

  3. P.H. Bardell, “Calculating the Effects of Linear Dependencies in m-Sequences Used as Test Stimuli,” IEEE Transactions on CAD, pp. 83-86, Jan. 1992.

  4. P.H. Bardell and W.H. McAnney, “Parallel Pseudo-random Sequences for Built-in Test,” in Proceedings International Test Conference, IEEE, 1984, pp. 302-308.

  5. P.H. Bardell and W.H. McAnney, “Pseudo-random Arrays for Built-in Tests,” IEEE Transactions on Computers, Vol. C-35,No. 7, pp. 653-658, 1986.

    Google Scholar 

  6. P. Bardell, W.H. McAnney, and J. Savir, Built-in Test for VLSI, New York: Wiley-Interscience, 1987.

    Google Scholar 

  7. R.W. Bassett, B.J. Butkus, S.L. Dingle, M.R. Faucher, P.S. Gillis, J.H. Panner, J.G. Petrovik, and D.L. Weather, “Low Cost Testing of High Density Logic Components,” in Proceedings International Test Conference, IEEE, 1989, pp. 550-557.

  8. R.K. Brayton, G.D. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Boston: Kluwer Academic Publishers, 1984.

    Google Scholar 

  9. F. Brglez, D. Bryan and K. Komzminski, “Combinational Profiles of Sequential Benchmark Circuits,” in Proceedings International Symposium on Circuits and Systems, IEEE, 1989, pp. 1929-1934.

  10. F. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran,” in Proceedings International Symposium On Circuits and Systems, IEEE, 1985, pp. 663-698.

  11. F. Brglez, C. Gloster, and G. Kedem, “Hardware-Based Weighted Random Pattern Generation for Boundary-Scan,” in Proceedings International Test Conference, IEEE, 1989, pp. 264-274.

  12. J.P. Hayes and A.D. Friedman, “Test Point Placement to Simplify Fault Detection,” IEEE Transactions on Computers, Vol. C-33, pp. 727-735, July 1974.

  13. S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, “Pattern Generation for a Deterministic BIST Scheme,” in Proceedings International Conference on Computer-Aided Design, IEEE, 1995, pp. 88-94.

  14. S. Hellebrand, H.-J. Wunderlich, and O.F. Haberl, “Generating Pseudo-Exhaustive Vectors for External Testing,” in Proceedings International Test Conference, IEEE, 1990, pp. 670-679.

  15. G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, and J. Rajski, “Logic BIST for Large Industrial Designs: Real Issues and Case Studies,” in Proceedings International Test Conference, IEEE, 1999, pp. 358-367.

  16. G. Kiefer and H.-J. Wunderlich, “Using BIST Control for Pattern Generation,” in Proceedings International Test Conference, IEEE, 1997, pp. 347-355.

  17. G. Kiefer and H.-J. Wunderlich, “Deterministic BIST with Multiple Scan Chains,” in Proceedings International Test Conference, IEEE, 1998, pp. 1057-1064.

  18. G. Kiefer and H.-J. Wunderlich, “Deterministic BIST with Partial Scan,” in Proceedings European Test Workshop, IEEE, 1999, pp. 110-116.

  19. S. Mukherji, L. Nguyen, D. Burek, and S. Baird, “IP/VC-Based Test Methodology (Part-1): A Case Study,” Digest of Papers International Workshop on Testing Embedded Core-Based Systems, IEEE, paper 1.2, pp. 1.9, 1998.

  20. B. Nadeau-Dostie, D. Burek, and A. Hassan, “Scan-BIST: A Multifrequency Scan-Based BIST Method,” IEEE Design & Test of Computers, Vol. 11,No. 1, pp. 7-17, 1994.

    Google Scholar 

  21. J. Rajski, N. Tamarapalli, and J. Tyszer, “Automated Synthesis of Large Phase Shifters for Built-In Self-Test,” in Proceedings International Test Conference, IEEE, 1998, pp. 1047-1056.

  22. B.H. Seiss, P.M. Trousborst, and M.H. Schulz, “Test Point Insertion for Scan-Based BIST,” in Proceedings European Test Conference, IEEE, 1991, pp. 253-262.

  23. Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 1999 edition.

  24. A. Ströle and H.-J. Wunderlich, “TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control,” IEEE Journal of Solid State Circuits, Vol. 26,No. 7, pp. 1056-1063, 1991.

    Google Scholar 

  25. N. Tamarapalli and J. Rajski, “Constructive Multi-Phase Test Point Insertion for Scan-Based BIST,” in Proceedings International Test Conference, IEEE, 1996, pp. 649-658.

  26. N.A. Touba and E.J. McCluskey, “Altering a Pseudo-Random Bit Sequence for Scan-Based BIST,” in Proceedings International Test Conference, IEEE, 1996, pp. 167-175.

  27. J.A. Waicukauski, E. Lindbloom, E.B. Eichelberger, and O.P. Forlenza, “A Method for Generating Weighted Random Test Patterns,” IBM Journal on Research and Development, Vol. 33,No. 2, pp. 149-161, March 1989.

    Google Scholar 

  28. H.-J. Wunderlich, “Self Test Using Unequiprobable Random Patterns,” in Proceedings 17th International Symposium on Fault-Tolerant Computing, IEEE, 1987, pp. 258-263.

  29. H.-J. Wunderlich and G. Kiefer, “Bit-Flipping BIST,” in Proceedings International Conference on Computer-Aided Design, IEEE, 1996, pp. 337-343.

  30. Y. Zorian, “Testing the Monster Chip,” IEEE Spectrum, pp. 54-60, July 1999.

  31. Y. Zorian, E.J. Marinissen, and S. Dey, “Testing Embedded-Core Based System Chips,” in Proceedings International Test Conference, IEEE, Washington, D.C, Oct. 1998, pp. 130-143.

    Google Scholar 

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Authors and Affiliations

  1. Computer Architecture Lab, University of Stuttgart, Breitwiesenstr. 20/22, 70565, Stuttgart, Germany

    Gundolf Kiefer

  2. Philips Research Laboratories, IC Design—Digital Design & Test, Prof. Holstlaan 4, 5656, AA, Eindhoven, The Netherlands

    Harald Vranken & Erik Jan Marinissen

  3. Computer Architecture Lab, University of Stuttgart, Breitwiesenstr. 20/22, 70565, Stuttgart, Germany

    Hans-Joachim Wunderlich

Authors
  1. Gundolf Kiefer
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  2. Harald Vranken
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  3. Erik Jan Marinissen
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  4. Hans-Joachim Wunderlich
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Kiefer, G., Vranken, H., Jan Marinissen, E. et al. Application of Deterministic Logic BIST on Industrial Circuits. Journal of Electronic Testing 17, 351–362 (2001). https://doi.org/10.1023/A:1012283800306

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