Abstract
This paper develops a new formal technique to verify the frequency response of analog circuits using global optimization techniques. Since simulation-based approaches are unable to cover the design space, there is a need for formal approaches to verify large circuits. Drawing parallels from the digital domain, the verification problem in the analog domain is modeled as a non-linear optimization problem and solved using global optimization techniques by ensuring that the implementation response is bounded within an envelope around the specification. We also address the problem of verifying frequency response under the influence of parameter variations. Direct as well as indirect techniques are illustrated using accurate frequency response models. Experimental results are presented to show the effectiveness of the proposed methodology.
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Seshadri, S., Abraham, J.A. Frequency Response Verification of Analog Circuits Using Global Optimization Techniques. Journal of Electronic Testing 17, 395–408 (2001). https://doi.org/10.1023/A:1012751118746
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DOI: https://doi.org/10.1023/A:1012751118746