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Fault Diagnosis for Linear Analog Circuits

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Abstract

This paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into a discrete signal flow graph, then constructs “diagnosing evaluators,” which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as active faults in OP's.

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Authors and Affiliations

  1. Department of Electronics Engineering, National Chiao Tung University, Hsin Chu, Taiwan, R.O.C

    Jun Weir Lin

  2. Department of Electronics Engineering, National Chiao Tung University, Hsin Chu, Taiwan, R.O.C

    Chung Len Lee & Chau Chin Su

  3. Department of Electrical Engineering, Chung Hwa University, Hsin Chu, Taiwan, R.O.C

    Jwu-E. Chen

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  1. Jun Weir Lin
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  2. Chung Len Lee
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  3. Chau Chin Su
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  4. Jwu-E. Chen
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Lin, J.W., Lee, C.L., Su, C.C. et al. Fault Diagnosis for Linear Analog Circuits. Journal of Electronic Testing 17, 483–494 (2001). https://doi.org/10.1023/A:1012816621144

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