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Configuring of Algorithms in Mapping into Hardware

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Abstract

The growing need for high-performance embedded processors on the reconfigurable computing platform increases the pressure for developing design methods and tools. One important issue in mapping algorithms into hardware is the configuring of algorithms to fit the particular hardware structure, the available area and configuration, together with time parameters. This paper presents an overview of a new synthesis method—the Iso-plane method—on the polytope model of algorithm to increase the parallelism and facilitate the configurability in regular array design via algebraic transformations as associativity and commutativity. The paper presents a variety of new regular and scalable array solutions with improved performance and better layout including motherboards with daughter boards.

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  1. SCISM, South Bank University, 103 Borough Road, London, SE1 0AA, UK

    Toomas P. Plaks

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Plaks, T.P. Configuring of Algorithms in Mapping into Hardware. The Journal of Supercomputing 21, 161–177 (2002). https://doi.org/10.1023/A:1013679420784

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