Abstract
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. In this paper we first discuss the general framework of the test generation algorithm followed by computational results. Comparison of results with SPICE simulations confirms the accuracy of this approach.
Similar content being viewed by others
References
M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Designs, Piscataway, NJ: IEEE Press, 1990.
N.D. Arora, K.V. Raol, and R. Schumann, “Modeling and Extraction of Interconnect Capacitance for Multilayer VLSI Circuits,” IEEE Trans. on Computer-Aided Design and Integrated Circuits and Systems, vol. 15, no. 1, pp. 58–67, January 1996.
L.C. Chen, S.K. Gupta, and M.A. Breuer, “A New Framework for Static Timing Analysis, Incremental Timing Analysis, and Timing Simulation,” in Proc. Asian Test Symp., 2000, pp. 102-107.
L.C. Chen, S.K. Gupta, and M.A. Breuer, “A New Gate Delay Model for Simultaneous Switching and its Applications,” in Proc. Design Automation Conf., June, 2001, pp. 289–294.
W.Y. Chen, S.K. Gupta, and M.A. Breuer, “Analytic Models for Crosstalk Delay and Pulse Analysis for Non-ideal Inputs,” in Proc. Int'l Test Conf., 1997, pp. 809–818.
W.Y. Chen, S.K. Gupta, and M.A. Breuer, “Test Generation in VLSI Circuits for Crosstalk Noise,” in Proc. Int'l Test Conf., 1998, pp. 641–650.
W.Y. Chen, S.K. Gupta, and M.A. Breuer, “Test Generation for Crosstalk-Induced Delay in Integrated Circuits,” in Proc. Int'l Test Conf., 1999, pp. 191–200.
W.Y. Chen, M.A. Breuer, and S.K. Gupta, “Timing Analysis for Test Generation for Crosstalk-Induced Delay in Integrated Circuits,” Computer Engineering Technical Report No. 99-04, Electrical Engineering–Systems Department, University of Southern California, April 1999.
N. Delorme, M. Bellevile, and J. Chilo, “Inductance and Capacitance Formulas for VLSI Interconnects,” Electronic Letters, vol. 32, no. 11, pp. 996–997, May 1996.
D.S. Gao, A.T. Yang, and S.M. Kang, “Modeling and Simulation of Interconnection Delays and Crosstalk in High-Speed Integrated Circuits,” IEEE Trans. on Circuits and Systems, vol. 37, pp.1–9, January 1990.
A.K. Goel, High-Speed VLSI Interconnections: Modeling, Analysis, and Simulation, New York: John Wiley &; Sons 1994.
A.K. Goel and Y.R. Huang, “Modeling of Crosstalk Among the GaAs VLSI Connections,” IEEE Proc. Part G, vol. 136, pp. 361–368, 1989.
P. Goel, “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits,” IEEE Trans. on Computer, vol. C-30, no.3, pp. 215–222, 1981.
N. Hedebstierna and K.O. Jeppson, “CMOS Circuit Speed and Buffer Optimization,” IEEE Trans. on Computer Aided Design, vol. 6, pp. 270–281, March 1987.
A.I. Kayssi, K.A. Sakallah, and T.M. Burks, “Analytical Transient Response of CMOS Inverters,” IEEE Trans. on Circuit and Systems, vol. 39, pp.43–45, January 1992.
K.T. Lee, C. Nordquist, and J.A. Abraham, “Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits,” in Proc. VLSI Test Symposium, 1998, pp. 34–39.
F. Moll and A. Rubio, “Spurious Signals in Digital CMOS VLSI Circuits: A Propagation Analysis,” IEEE Trans. on Circuits and Systems –II: Analog and Digital Signal Processing, vol. 39, no. 10, pp. 749–752, October 1992.
F. Moll and A. Rubio, “Methodology of Detection of Spurious Signals in VLSI Circuits,” in Proc. Europe Test Conference, 1993, pp. 491–496.
A. Rubio and R. Anglada, “An Approach to Crosstalk Effect Analysis and Avoidance Techniques in Digital CMOS VLSI Circuits,” Int'l. Journal of Electronics, vol. 65, no. 1, pp. 3–17, 1988.
A. Rubio, N. Itazaki, X. Xu, and K. Kinoshita, “An Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 3, pp.387–394, March 1994.
S. Voranantakul and J.L. Prince, “Crosstalk Analysis for High-Speed Pulse Propagation in Lossy Electrical Interconnections,” IEEE Trans. on Components, Hybrids, and Manufacturing Technology, vol. 16, no. 1, pp. 127–136, February 1993.
R.K Watts, Submicron Integrated Circuit, NewYork: Wiley, pp. 317–318, 1989.
H. You and M. Soma, “Crosstalk andTransient Analysis of High-Speed Interconnects and Packages,” IEEE Trans. on Solid State Circuits, vol. 26, pp. 319–330, March 1991.
A.E. Zain and S. Chowdhury, “An Analytical Method for Finding the Maximum Crosstalk in Lossless-Coupled Transmission Lines,” Proc. Int'l Conf. on Computed Aided Design, 1992, pp. 443-448.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Chen, WY., Gupta, S.K. & Breuer, M.A. Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. Journal of Electronic Testing 18, 17–28 (2002). https://doi.org/10.1023/A:1013771821826
Issue Date:
DOI: https://doi.org/10.1023/A:1013771821826