Abstract
Several types of Decision Diagrams (DDs) have been proposed for the verification of Integrated Circuits. Recently, word-level DDs like BMDs, *BMDs, HDDs, K*BMDs and *PHDDs have been attracting more and more interest, e.g., by using *BMDs and *PHDDs it was for the first time possible to formally verify integer multipliers and floating point multipliers of “significant” bitlengths, respectively.
On the other hand, it has been unknown, whether division, the operation inverse to multiplication, can be efficiently represented by some type of word-level DDs. In this paper we show that the representational power of any word-level DD is too weak to efficiently represent integer division. Thus, neither a clever choice of the variable ordering, the decomposition type or the edge weights, can lead to a polynomial DD size for division.
For the proof we introduce Word-Level Linear Combination Diagrams (WLCDs), a DD, which may be viewed as a “generic” word-level DD. We derive an exponential lower bound on the WLCD representation size for integer dividers and show how this bound transfers to all other word-level DDs.
Similar content being viewed by others
References
R.I. Bahar, E.A. Frohm, C.M. Gaona, G.D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, “Algebraic decision diagrams and their application,” in Int'l Conf. on CAD, 1993, pp. 188-191.
B. Becker, R. Drechsler, and R. Enders, “On the computational power of bit-level and word-level decision diagrams,” in ASP Design Automation Conf., 1997, pp. 461-467.
R.E. Bryant, “Graph-based algorithms for Boolean function manipulation,” IEEE Trans. on Comp., Vol. 35, No. 8, pp. 677-691, 1986.
R.E. Bryant, “On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication,” IEEE Trans. on Comp., Vol. 40, pp. 205-213, 1991.
R.E. Bryant, “Binary decision diagrams and beyond: Enabeling techniques for formal verification,” in Int'l Conf. on CAD, 1995, pp. 236-243.
R.E. Bryant and Y.-A. Chen, “Verification of arithmetic functions with binary moment diagrams,” in Design Automation Conf., 1995, pp. 535-541.
Y.-A. Chen and R.E. Bryant, “*PHDD: An efficient graph representation for floating point circuit verification,” in Int'l Conf. on CAD, 1997, pp. 2-7.
E.M. Clarke, M. Fujita, and X. Zhao, “Hybrid decision diagrams-Overcoming the limitations of MTBDDs and BMDs,” in Int'l Conf. on CAD, 1995, pp. 159-163.
E.M. Clarke, K.L. McMillan, X. Zhao, M. Fujita, and J. Yang, “Spectral transforms for large Boolean functions with application to technology mapping,” in Design Automation Conf., 1993, pp. 54-60.
R. Drechsler, B. Becker, and S. Ruppertz, “K*BMDs: A new data structure for verification,” in European Design & Test Conf., 1996, pp. 2-8.
R. Drechsler, A. Sarabi, M. Theobald, B. Becker, and M.A. Perkowski, “Efficient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams,” in Design Automation Conf., 1994, pp. 415-419.
U. Kebschull, E. Schubert, and W. Rosenstiel, “Multilevel logic synthesis based on functional decision diagrams,” in European Conf. on Design Automation, 1992, pp. 43-47.
Y.-T. Lai and S. Sastry, “Edge-valued binary decision diagrams for multi-level hierarchical verification,” in Design Automation Conf., 1992, pp. 608-613.
S. Malik, A.R. Wang, R.K. Brayton, and A.L. Sangiovanni-Vincentelli, “Logic verification using binary decision diagrams in a logic synthesis environment,” in Int'l Conf. on CAD, 1988, pp. 6-9.
M. Nakanishi, “An exponential lower bound on the size of a binary moment diagram representing division,” Master's Thesis, Osaka University, Japan, 1998.
C. Scholl, B. Becker, and T.M. Weis, “Word-level decision diagrams, WLCDs and division,” in Int'l Conf. on CAD, 1998, pp. 672-677.
J.S. Thathachar, “On the limitations of ordered representations of functions,” in Computer Aided Verification, 1998, LNCS, Vol. 1427.
S. Waack, “On the descriptive and algorithmic power of parity ordered binary decision diagrams,” in Symp. on Theoretical Aspects of Comp. Science, 1997, LNCS, Vol. 1200.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Scholl, C., Becker, B. & Weis, T. On WLCDs and the Complexity of Word-Level Decision Diagrams—A Lower Bound for Division. Formal Methods in System Design 20, 311–326 (2002). https://doi.org/10.1023/A:1014702331828
Issue Date:
DOI: https://doi.org/10.1023/A:1014702331828