Skip to main content
SpringerLink
Log in

Enhanced Reduced Pin-Count Test for Full-Scan Design

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-RPCT for full-scan design, as well as for full-scan core-based design.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. R.W. Bassett, S.L. Dingle, P.S. Gillis, J.G. Petrovick, B.J. Butkus, M.R. Faucher, J.H. Panner, and D.L. Wheater, “Low Cost Testing of High Density Logic Components,” in Proceedings International Test Conference, 1989, Washington, D.C., pp. 550–557.

  2. R.W. Bassett, M.E. Turner, J.H. Panner, P.S. Gillis, S.F. Oakland, and D.W. Stout, “Boundary-Scan Design Principles for Efficient LSSD ASIC Testing,” IBM Journal on Research and Development, vol. 34, no. 2/3, pp. 339–354, 1990.

    Google Scholar 

  3. A. Chandra and K. Chakrabarty, “Test Data Compression for System-on-a-Chip Using Golomb Codes,” in Proceedings VLSI Test Symposium, 2000, Montreal, Canada, pp. 113–120.

  4. T.G. Foote, D.E. Hoffman, W.V. Huott, T.J. Koprowski, M.P. Kusko, and B.J. Robbins, “Testing the 500-MHz IBM S/390 Microprocessor,” IEEE Design & Test of Computers, pp. 83–89, July-Sept. 1998.

  5. P.S. Gillis, T.S. Guzowski, B.L. Keller, and R.H. Kerr, “Test Methodologies and Design Automation for IBM ASICs,” IBM Journal on Research and Development, vol. 40, no. 4, pp. 461–474, 1996.

    Google Scholar 

  6. P. Gillis, F. Woytowich, K. McCauley, and U. Baur, “Delay Test of Chip I/Os UsingLSSDBoundary Scan,” in Proceedings International Test Conference, 1998, Washington, D.C., pp. 83–90.

  7. D. Heidel, S. Dhong, P. Hofstee, M. Immediato, K. Nowka, J. Silberman, and K. Stawiasz, “High Speed Serializing/Deserializing Design-for-Test Method for Evaluating a 1 GHz Microprocessor,” in Proceedings VLSI Test Symposium, 1998, Monterey, CA, pp. 234–238.

  8. W.V. Huott, T.J. Koprowski, B. J. Robbins, M.P. Kusko, S.V. Pateras, D.E. Hoffman, T.G. McNamara, and T.J. Snethen, “Advanced Microprocessor Test Strategy and Methodology,” IBM Journal on Research and Development, vol. 41, no. 4/5, pp. 611–628, 1997.

    Google Scholar 

  9. IEEE, “Panel Session: DFT-Focused Chip Testers: What Can They Really Do ?,” in Proceedings International Test Conference, 2000, Atlantic City, NJ, pp. 1119–1122.

  10. IEEE Std. 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990.

  11. A. Jas, J. Ghosh-Dastidar, and N.A. Touba, “Scan Vector Compression/ Decompression Using Statistical Coding,” in Proceedings VLSI Test Symposium, 1999, Dana Point, CA, pp. 114–12.

  12. A. Jas and N.A. Touba, “Test Vector Decompression via Cyclical Scan Chains and its Application to Testing Core-Based Designs,” in Proceedings International Test Conference, 1998, Washington, D.C., pp. 458–464.

  13. E.J. Marinissen, R. Kapur, and Y. Zorian, “On using IEEE P1500 SECT for Test Plug-n-Play,” in Proceedings International Test Conference, 2000, Atlantic City, NJ, pp. 770–777.

  14. Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 1999 edition and 2000 update.

  15. N. Tendolkar, R. Molyneaux, C. Pyron, and R. Raina, “At-Speed Testing of Delay-Faults for Motorola's MPC7400, A PowerPC Microprocessor,” in Proceedings VLSI Test Symposium, 2000, Montreal, Canada, pp. 3–8.

  16. N. Zacharia, J. Rajski, and J. Tyszer, “Decompression of Test Data Using Variable-Length Seed LFSRs,” in Proceedings VLSI Test Symposium, 1995, Princeton, NJ, pp. 426–433.

  17. Y. Zorian, “Testing the Monster Chip,” IEEE Spectrum, pp. 54–60, July 1999.

  18. Y. Zorian, E.J. Marinissen, and S. Dey, “Testing Embedded-Core Based System Chips,” in Proceedings International Test Conference, 1998, Washington, D.C., pp. 130–143.

Download references

Author information

Authors and Affiliations

  1. Philips Research Laboratories, IC Design—Digital Design & Test, Prof. Holstlaan 4, M/S WAY-41, 5656 AA, Eindhoven, The Netherlands

    Harald Vranken

  2. Electronic Design & Tools, Philips Research Laboratories, Prof. Holstlaan 4, M/S WAY-31, 5656 AA, Eindhoven, The Netherlands

    Tom Waayers

  3. IC Development—Design for Test, Philips Semiconductors, 2, Rue de la Girafe, 14079, Caen Cedex 5, France

    Hervé Fleury

  4. Test & Product Engineering, Philips Semiconductors, 2, Rue de la Girafe, 14079, Caen Cedex 5, France

    David Lelouvier

Authors
  1. Harald Vranken
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Tom Waayers
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Hervé Fleury
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. David Lelouvier
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Vranken, H., Waayers, T., Fleury, H. et al. Enhanced Reduced Pin-Count Test for Full-Scan Design. Journal of Electronic Testing 18, 129–143 (2002). https://doi.org/10.1023/A:1014989408897

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1014989408897

Search

Navigation