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Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

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Abstract

A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.

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  1. Computer Engineering Research Center, Department of Electrical and Computer Engineering, Engineering Science Building, University of Texas at Austin, Austin, TX, 78712-1084, USA

    Abhijit Jas & Nur A. Touba

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  1. Abhijit Jas
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  2. Nur A. Touba
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Jas, A., Touba, N.A. Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor. Journal of Electronic Testing 18, 503–514 (2002). https://doi.org/10.1023/A:1016505926570

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