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Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

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Abstract

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.

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  1. Center for Integrated Circuits & Systems, The University of Texas at Dallas, Richardson, TX, 75083-0688, USA

    Mehrdad Nourani & Amir Attarha

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  1. Mehrdad Nourani
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  2. Amir Attarha
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Nourani, M., Attarha, A. Signal Integrity: Fault Modeling and Testing in High-Speed SoCs. Journal of Electronic Testing 18, 539–554 (2002). https://doi.org/10.1023/A:1016514129296

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