Abstract
In this paper, a method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based System-On-Chip (SOC) designs is presented. The primary objective for concurrent SOC test is to reduce test application time under the constraints of SOC pins and peak power consumption. The methodology used in this paper is not limited to any specific Test Access Mechanism (TAM). Additionally, it can also be applied to SOC budgeting at design phase to predict a tradeoff between test application time and SOC pins needed. The contribution of this paper is the formulation of the problem as a well-known 2-dimensional bin-packing problem. A best-fit heuristic algorithm is adopted to achieve optimal solution.
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Huang, Y., Cheng, WT., Tsai, CC. et al. On Concurrent Test of Core-Based SOC Design. Journal of Electronic Testing 18, 401–414 (2002). https://doi.org/10.1023/A:1016541407006
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DOI: https://doi.org/10.1023/A:1016541407006