Abstract
This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.
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References
M. Berkelaar, lp solve, version 3.2, Eindhoven University of Technology, The Netherlands, ftp://ftp.ics.ele.tue.nl/ pub/lp solve.
S. Bhatia, T. Gheewala, and P. Varma, “AUnifying Methodology for Intellectual Property and Custom Logic Testing, ” in Proc. 1996 Int. Test Conf., Oct. 1996, pp. 639–648.
K. Chakrabarty, “Design of System-on-a-Chip Test Access Architectures Using Integer Linear Programming, ” in Proc. 18th VLSI Test Symp., May 2000, pp. 127–134.
K. Chakrabarty, “Design of System-on-a-Chip Test Access Architectures Under Place-and-Route and Power Constraints, ” in Proc. 37th Design Automation Conf., June 2000, pp. 432–437.
K. Chakrabarty, R. Mukherjee, and A. Exnicios, “Synthesis of Transparent Circuits for Hierarchical and System-on-a-Chip Test, ” in Proc. IEEE International Conference on VLSI Design, Jan. 2001, pp. 431–436.
I. Ghosh, S. Dey, and N.K. Jha, “A Fast and Low Cost Testing Technique for Core-Based System-Chips, ” IEEE Trans. onCAD, vol. 19, no. 8, pp. 863–877, Aug. 2000.
I. Ghosh, N.K. Jha, and S. Dey, “A Low Overhead Design for Testability and Test Generation Technique for Core-Based Systems-on-a-Chip, ” IEEE Trans. on CAD, vol. 18, no. 11, pp. 1661–1676, Nov. 1999.
E. Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, and C. Wouters, “AStructured and Scalable Mechanism for Test Access to Embedded Reusable Cores, ” in Proc. 1998 Int. Test Conf., Nov. 1998, pp. 284–293.
M. Nourani and C.A. Papachristou, “Structural Fault Testing of Embedded Cores Using Pipelining, ” Journal of Electronic Testing: Theory and Applications, vol. 15, pp. 129–144, 1999.
T. Ono, K. Wakui, H. Hikima, Y. Nakamura, and M. Yoshida, “Integrated and Automated Design-for-Testability Implementation for Cell-Based Ics, ” in Proc. 6th Asian Test Symp., Nov. 1997, pp. 122–125.
S. Ravi, G. Lakshminarayana, and N.K. Jha, “Testing of Core-Based Systems-on-a-Chip, ” IEEE Trans. on CAD, vol. 20, no. 3, pp. 426–439, March 2001.
N.A. Touba and B. Pouya, “Testing Embedded Cores Using Partial Isolation Rings, ” in Proc. 15th VLSI Test Symp., May 1997, pp. 10–16.
P. Varma and S. Bhatia, “AStructured Test Re-Use Methodology for Core-Based System Chips, ” in Proc. 1996 Int. Test Conf., Oct. 1998, pp. 294–302.
L. Whetsel, “An IEEE 1149.1 Based Test Access Architecture for ICs with Embedded Cores, ” in Proc. 1997 Int. Test Conf., Nov. 1997, pp. 69–78.
T. Yoneda and H. Fujiwara, “A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability, ” in Proc. 10th Asian Test Symp., Nov. 2001, pp. 193–198.
Y. Zorian, E.J. Marinissen, and S. Dey, “Testing Embedded-Core Based System Chips, ” in Proc. 1998 Int. Test Conf., Oct. 1998, pp. 130–143.
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Yoneda, T., Fujiwara, H. Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. Journal of Electronic Testing 18, 487–501 (2002). https://doi.org/10.1023/A:1016553809732
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DOI: https://doi.org/10.1023/A:1016553809732