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Reconfigurable Testbed for Interference Cancellation in DS-CDMA Systems

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Abstract

Interference cancellation techniques fordirect-sequence code division multiple access (DS-CDMA)systems have the potential to provide significantcapacity gains over conventional matched filterreceivers. The complexity of the signal processingalgorithms for interference cancellation often requiresprocessing speeds that are beyond that of currentdigital signal processor (DSP) technology. In thispaper, we show that this difficulty can be overcome bypartitioning the algorithmic functionality into two coretechnologies (field programmable gate arrays [FPGA] andDSP devices) based on processing speed requirements. We give implementation proofs via a testbedthat allows a dynamic reconfiguration among constituentreceivers being considered. Experimental results on theperformance of the receivers are presented.

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Authors
  1. Ivan Seskar
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  2. Narayan B. Mandayam
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  3. Paul Hatrack
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Seskar, I., Mandayam, N.B. & Hatrack, P. Reconfigurable Testbed for Interference Cancellation in DS-CDMA Systems. International Journal of Wireless Information Networks 6, 37–47 (1999). https://doi.org/10.1023/A:1018879216442

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