Abstract
In this paper, we propose a novel augmenting and partitioning scheme for constructing multistage interconnection networks (MINs) with improved fault-tolerant capabilities. We first propose a partitioning scheme to construct and analyze partitioned MINs (PMINs). A simulation method is developed, based on the stuck-at fault model, to evaluate dynamic full access (DFA) and average number of passes in PMINs. We then propose an augmenting scheme to construct augmented partitioned MINs (APMINs) with further enhanced fault-tolerant capabilities. Simulation analysis of APMINs, based on the switch level fault model, showed that the proposed scheme significantly improves the fault-tolerant capability of MINs. Finally, the effectiveness of the proposed scheme is evaluated with respect to cost, DFA, locality, and average path length.
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References
G. Adams III, D.P. Agrawal and H.J. Siegel, A survey and comparison of fault-tolerant interconnection networks, IEEE Transactions on Computers 6 (1987) 14-27.
G. Adams III and H.J. Siegel, The extra stage cube: A fault-tolerant interconnection network for supersystems, IEEE Transactions on Computers 5 (1982) 397-408.
D.P. Agrawal and J.-S. Leu, Dynamic accessibility testing and path length optimization of multistage interconnection networks, IEEE Transactions on Computers 3 (1985) 255-266.
T.Y. Feng, A survey of interconnection networks, Computers 14(12) (1981) 12-27.
K. Hwang and F. Briggs, Computer Architecture and Parallel Processing (Mcgraw-Hill, New York, 1984).
V.P. Kumar and S.M. Reddy, On fault-tolerant multistage interconnection networks, in: Proc. of International Conference on Parallel Processing (1984) pp. 155-164.
V.P. Kumar and S.M. Reddy, Augmented shuffle exchange multistage interconnection networks, IEEE Transactions on Computers 6 (1987) 30-40.
V.P. Kumar and S.J. Wang, Dynamic full access in fault tolerant multistage interconnection networks, in: Proc. of International Conference on Parallel Processing (1990) pp. I621-I630.
D.H. Lawrie, Access and alignment of data in an array processor, IEEE Transactions on Computers 12 (1975) 99-109.
E. Opper and M. Malek, Multiple fault-diagnosis of SW-Banyan networks, in: Proc. Fault-Tolerant Computing Symposium (June 1983) pp. 446-449.
H.J. Siegel and R.J. McMillen, The multistage cube: A versatile interconnection network, IEEE Transactions on Computers 12 (1981) 65-67.
N. Tzeng, P. Yew and C. Zhu, A fault-tolerant for multistage interconnection networks, in: 12th International Symposium on Computer Architecture (June 1985) pp. 368-375.
A. Varma and C.S. Raghavendra, Fault-tolerant routing in multistage interconnection networks, IEEE Transactions on Computers 3 (1989) 385-393.
C.W. Weiss, Bounds on the length of terminal stuck-fault tests, IEEE Transactions on Computers 3 (1972) 305-309.
C. Wu and T.Y. Feng, On a class of multistage interconnection networks, IEEE Transactions on Computers 8 (1980) 1145-1155.
C. Wu and T.Y. Feng, The reverse-exchange interconnection networks, IEEE Transactions on Computers 9 (1980) 801-811.
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Mahgoub, I., Huang, CJ. A novel scheme to improve fault-tolerant capabilities of multistage interconnection networks. Telecommunication Systems 10, 45–66 (1998). https://doi.org/10.1023/A:1019102613662
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DOI: https://doi.org/10.1023/A:1019102613662