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Performance of a large multicast ATM switch

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Abstract

In this paper, we present the design of a large self-routing multicast ATM switch. The switch consists of a sorting network followed by a 3-stage routing network. We first present a simple design of a large sorting network built using small sized shared memory that can be used as a building block for a large sorting network. Small sized shared memory is also used in the 3-stage routing network making the switch modular and easy to implement using current VLSI technology. As the network uses shared memory modules, multicasting functionality is easily built into the network. The performance of the proposed network is compared with an equivalent completely shared memory switch using computer simulations under bursty traffic model. The results show that the proposed network has better performance in terms of cell loss ratio than the completely shared memory switch under moderate to heavy traffic load (0.6 ≤ effective offered load ≤ 1.2). Furthermore, multicast cell delays are drastically improved.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Clarkson University, P.O. Box 5720, Potsdam, NY 13699, USA

    Neeraj K. Sharma

  2. Department of Computer Science and Computer Engineering, La Trobe University, Bundoora, Victoria, 3083, Australia

    Julian D. Ho

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  1. Neeraj K. Sharma
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  2. Julian D. Ho
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Sharma, N.K., Ho, J.D. Performance of a large multicast ATM switch. Telecommunication Systems 13, 453–467 (2000). https://doi.org/10.1023/A:1019116728142

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