Abstract
Communication satellites frequently employ downlink spot beams to gain efficiency and flexibility. This process may change the output buffering behavior of a packet switch because of the extra overhead involved in beam‐forming (the dwell setup time). This paper investigates the effect of dwell setup time on the output buffer design. Four theoretical models, including single buffer systems, multiple buffer systems with fixed beam forming pattern, multiple buffer systems with adaptive beam forming pattern and multiple buffer systems with fixed time allocation, are considered. Analytical queuing solutions are obtained for all the cases except for the exhaustive and gated adaptive multiple buffer systems, in which only the state transition equations are given. NASA's proposed MCSPS (Multi‐channel Communication Signal Processing Satellite) architecture is used as a numerical example.
Similar content being viewed by others
References
G.B. Alaria et al., On-board processor for a TST/SS-TDMA telecommunications system, ESA Journal 9 (1985).
O.J. Boxma, Models of two queues: A few new views, in: Teletraffic Analysis and Computer Performance Evaluation, eds. J.W. Cohen et al. (Elsevier Science Publishers, 1986).
J.S.C. Chen and T.E. Stern, Throughput analysis, optimal buffer allocation, and traffic imbalance study of a generic nonblocking packet switch, IEEE Journal on Selected Areas in Communications 9(3) (April 1991) 439–449.
D.M. Chitre, The role of satellite communication in the ISDN era, International Journal of Satellite Communications 10 (1992) 209–215.
D.M. Chitre and W.S. Oei, Architectures for the Intelsat ISBN-compatible satellite communications network, International Journal of Satellite Communications 10 (1992) 217–225.
F. Faris et al., On-board B-ISDN fast packet switching architectures, NASA Contract NAGW-4528 Final Report, NASA CR-189144 (1993).
R. Händel and M.N. Huber, Integrated Broadband Network (Addison-Wesley, Reading, MA, 1992).
J.L. Harrold, J.M. Budinger and G.H. Stevens, On-board switching and processing, Proceedings of IEEE 78(7) (July 1990) 1206–1213.
M.G. Hluchyj and M.J. Karol, Queueing in high performance packet switching, IEEE Journal on Selected Areas in Communications 6(9) (December 1988) 1587–1597.
T. Inukai and D.J. Shyy, Technology support for digital systems technology development, Task Order 1: Information switching processor contention analysis and control, NASA Contract NAS3–25933, Task 1 Final Report, NASA CR-191143 (1993).
D. Ivancic et al., Destination directed packet switch architecture for a geostationary communication satellite network, in: Proc. 43rd World Space Congress (1992).
M.J. Karol, M.G. Hluchyj and S.P. Morgan, Input versus output queueing on a space-division packet switch, IEEE Transactions on Communications 35(12) (December 1987) 1347–1356.
L. Kleinrock, Queueing Systems. Vol. 1: Theory (Wiley, New York, 1975).
R. Moat, ACTS baseband processing, in: Proc. IEEE GLOBECOM (1986).
D.J. Shyy and T. Inukai, Technology support for digital systems technology development, Task Order 2: Information switching processor congestion control, NASA Contract NAS3–25933, Task 2 Final Report, NASA CR-191130 (1993).
D.J. Shyy, Data generation for destination directed packet switch, NASA Contract NAS3–25933, Task 4 Final Report (1993).
H. Takagi, Analysis of Polling Systems (MIT Press, 1986).
H. Takagi, Queueing analysis of polling models: an update, in: Stochastic Analysis of Computer and Communication Systems, ed. H. Takagi (Elsevier Science Publishers, 1990).
R.W. Wolff, Stochastic Modeling and the Theory of Queues (Prentice-Hall, Englewood Cliffs, NJ, 1989).
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Chu, P.P. The impact of beam forming on the performance of an on‐board output buffer. Telecommunication Systems 8, 229–256 (1997). https://doi.org/10.1023/A:1019165505485
Issue Date:
DOI: https://doi.org/10.1023/A:1019165505485