Abstract
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimization and simulation, HDL-based synthesis, etc. is currently a field of increasing research activity. This paper describes a circuit partitioning algorithm which mixes Simulated Annealing (SA) and Tabu Search (TS) heuristics. The goal of such an algorithm is to obtain a balanced distribution of the target circuit among the processors of the multicomputer allowing a parallel CAD application for Test Pattern Generation to provide good efficiency. The results obtained indicate that the proposed algorithm outperforms both a pure Simulated Annealing and a Tabu Search. Moreover, the usefulness of the algorithm in providing a balanced workload distribution is demonstrated by the efficiency results obtained by a topological partitioning parallel test-pattern generator in which the proposed algorithm has been included. An extented algorithm that works with general graphs to compare our approach with other state of the art algorithms has been also included.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
E. Aarts and J.Korst, Simulated Annealing and Boltzmann Machines. A Stochastic Approach to Combinatorial Optimization and Neural Computing, John Wiley & Sons: New York, 1990.
C.J. Alpert and A. Kahng, “Recent developments in netlist partitioning: A survey,” Integration: The VLSI Journal, vol. 19, no. 1/2, pp. 1–81, 1995.
A.A. Andreatta and C.C. Ribeiro, “A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits,” Annals of Operations Research, vol. 50, pp. 1–36, 1994.
S. Areibi and A. Vannelli, “Advanced search technique for circuit partitioning,” in DIMACS Series in Discrete Mathematics and Theoretical Computer Science, vol. 16, pp. 77–98, 1993.
P. Banerjee, Parallel Algorithms for VLSI Computer Aided Design, Prentice Hall; Englewoods Cliffs, NJ, 1994.
F. Brglez and H. Fujiwara, “Neural netlist of ten combinational benchmark circuits and a target translator in FORTRAN,” in Proc. IEEE Int. Symp. Circuits Syst., Special Session ATPG, 1985.
J.A. Chandy and P. Banerjee, “A parallel circuit-partitioned algorithm for timing-driven standard cell placement,” Journal of Parallel and Distributed Computing, vol. 57, pp. 64–90, 1999.
J. Cong and M. Smith, “A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design,” in Proc. ACM/IEEE Design Automation Conference, 1993, pp. 755–760.
K.A. Dowsland, “Simulated annealing,” in Modern Heuristic Techniques for Combinatorial Problems, C.R. Reeves (Ed.), Blackwell: London, 1993, pp. 20–69.
C. Fiduccia and R. Mattheyses, “A linear time heuristic for improving network partitions,” in Proc. 19th IEEE Design Automation Conference, pp. 175–181, 1982.
M.R. Garey and D.S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W.H. Freeman: San Francisco, 1979.
C. Gil and J. Ortega, “A parallel test pattern generator based on Reed-Muller spectrum,” in EuromicroWorkshop on Parallel and Distributed Processing, IEEE, pp. 199–204, 1997.
C. Gil and J. Ortega, “Algebraic test-pattern generation based on the Reed-Muller spectrum,” IEE Proceding Computers and Digital Techniques, vol. 145, no. 4, pp. 308–316, 1998.
C. Gil, J. Ortega, and M.G. Montoya, “Parallel VLSI test in a shared memory multiprocessors,” Concurrency: Practice and Experience, vol. 12, no. 5, pp. 311–326, 2000.
J. Gilbert, G. Miller, and S. Teng, “Geometric mesh partitioning: Implementation and experiments,” in Proceedings of International Parallel Processing Symposium, 1995.
F. Glover and M. Laguna, “Tabu Search,” in Modern Heuristic Techniques for Combinatorial Problems, C.R. Reeves (Ed.), Blackwell: London, 1993, pp. 70–150.
T. Goehring and Y. Saad, “Heuristic algorithms for automatic graph partitioning,” Technical Report UMSI-94-29. University of Minnesota Supercomputing Institute, 1994.
S.W. Hadley, B.L. Mark, and A. Vanelli, “An efficient eigenvector approach for finding netlist partitions,” IEEE Trans. on Computer-Aided Dessign, vol. 11, no. 7, pp. 885–892, 1992.
B. Hendrickson and R. Leland, “A multilevel algorithm for partitioning graphs,” in Proceedings Supercomputing '95, ACM Press, 1995.
D.S. Johnson, C.R. Aragon, and L.A. McGeogh, “Optimization by simulated annealing: An experimental evaluation, Part I: Graph partitioning,” Operations Research, vol. 37, pp. 865–892, 1989.
G. Karypis and V. Kumar, “Multilevel K-way partitioning scheme for irregular graphs,” Journal of Parallel and Distributed Computing, vol. 48, no. 1, pp. 96–129, 1998.
B.W. Kernighan and S. Lin, “An efficient heuristic procedure for partitioning graphics,” The Bell Sys. Tech. Journal, pp. 291–307, 1970.
R.H. Klenke, R.D. Williams, and J.H. Aylor, “Parallel-processing techniques for automatic test pattern generation,” IEEE Computer, pp. 71–84, 1992.
V. Kumar, A. Grama, A. Gupta, and G. Karypis, Introduction to Parallel Computing. Design and Analysis of Algorithms, The Benjamin/Cummings Publishing, 1994.
V. Kumar, A. Grama, and V.N. Rao, “Scalable load balancing techniques for parallel computers,” Journal of Distributed and Parallel Computing, vol. 22, pp. 60–79, 1994.
C.R. Reeves, “Genetic algorithms,” in Modern Heuristic Techniques for Combinatorial Problems, C.R. Reeves (Ed.), Blackwell: London, 1993, pp. 151–196.
L.A. Sanchis, “Multiple-way network partitioning with different cost functions,” IEEE Trans. on Comp., vol. 42, no. 12, pp. 1500–1504, 1993.
K. Schloegel, G. Karypis, and V. Kumar, “Graph partitioning for high performance scientific simulations,” in CRPC Parallel Computing Handbook, Morgan Kaufmann: San Matio, CA, 2000.
I. Shperling and E.J. McCluskey, “Circuit segmentation for pseudo-exhhaustive testing via simulated annealing,” in International Test Conference IEEE, 1987.
A.J. Soper, C. Walshaw, and M. Cross, “A combined evolutionary search and multilevel optimisation approach to graph partitioning,” Mathematics Research Report 00/IM/58, University of Greenwich, 2000.
C. Walshaw and M. Cross, “Mesh partitioning: A multilevel balancing and refinement algorithm,” SIAM J. Sci. Comput., vol. 22, no. 1, pp. 63–80, 2000.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Gil, C., Ortega, J., Montoya, M. et al. A Mixed Heuristic for Circuit Partitioning. Computational Optimization and Applications 23, 321–340 (2002). https://doi.org/10.1023/A:1020551011615
Issue Date:
DOI: https://doi.org/10.1023/A:1020551011615