Abstract
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach.
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D.M.H. Walker, Yield Simulation for Integrated Circuits, Boston, MA: Kluwer Academic Publishers, 1987. Soon-Jyh Chang was born in Taiwan 1969. He received his M.S. degree in Electronic Engineering from National Chiao-Tung University, Hsin-Chu, Taiwan, in 1996. He is currently working towards his Ph.D. degree at NCTU. His research interests including test generation and design for testability for analog and mixed-signal circuits. Chung-Len Lee received BS degree in electrical engineering from NationalTaiwan University,Taiwan, R.O.C., in 1968.Heobtained his M.S. and Ph.D. Degree in Electrical Engineering, Carnegie-Mellon University, U.S.A., in 1971 and 1975 respectively. From 1975, he has been a professor of Electronic Engineering at National Chiao-Tung University in Taiwan, and was the director of Semiconductor Research Center of the university in the period of 1980–1983. From 1989 to present, he is the director of the Training Center for Submicron Professionals of the university and supervised more than 100 M.S. and Ph.D. students to complete their thesis work that result in more than 200 journal and conference papers published. His research interests are in the area of semiconductor processes, material and devices, integrated circuit design, VLSI testing, and integrated optics. He has been involved in various technical activities in the above areas in Taiwan as well as in Asia. He is a senior member of IEEE and member of editorial board, Journal of Electronic Testing: Theory, and Application. Jwu E. Chen received BS, MS, and Ph.D. degrees in electronic engineering from National Chiao-Tung University, Taiwan, in 1984, 1986 and 1990 respectively. Presently, he is an sssociate professor of Electrical Engineering of Chung-Hua University, Taiwan. His research interests are in reliability, fault tolerant and test quality of circuits.
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Chang, SJ., Lee, C.L. & Chen, J.E. Structural Fault Based Specification Reduction for Testing Analog Circuits. Journal of Electronic Testing 18, 571–581 (2002). https://doi.org/10.1023/A:1020892721493
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DOI: https://doi.org/10.1023/A:1020892721493