Abstract
In state-of-the-art multimedia compression standards, arithmetic coding is widely used as a powerful entropy compression method. In the MPEG-4 standard a specific 4-symbol, multiple-context arithmetic coder is used for wavelet based image compression. In this paper we present a first-of-a-kind architecture capable of processing close to 1 symbol per cycle, managing multiple context in a simple, yet cost-efficient manner. We explain the need for such an architecture, develop the algorithm and propose an efficient implementation. The characteristics of the architecture are detailed and a comparison with other alternatives is presented. This architecture has been synthesized achieving a maximum speed of 170 MHz, equivalent to 340 Mbits/s.
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Osorio, R.R., Vanhoof, B. High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 33, 267–275 (2003). https://doi.org/10.1023/A:1022123829466
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DOI: https://doi.org/10.1023/A:1022123829466