Abstract
In this paper, an architecture for real-time digital HDTV video decoding is presented. Our architecture is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. The decoding datapath is synchronized at the block (8 × 8 pixels) level. Unlike other decoding approaches such as the slice bar decoding method and the cross-divide method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. In comparison to data-flow approaches, our method eliminates the complexity associated with tagged data operations. Our anchor picture storage is organized to minimize page-breaks during memory accesses. Simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1,920 × 1,080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbps.
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References
ISO/ICE 13818-2, Generic Coding of Moving Pictures and Associated Audio Information: Video, Nov. 1994.
A. Cugnini and R. Shen, "MPEG-2 Video Decoder for the Digital HDTV Grand Alliance System," IEEE Trans. on Consumer Electronics, vol. 41, no. 3, 1995, pp. 748-753.
C.L. Lee, C.S. Ho, S.-F. Tsai, C.-F. Wu, J.-Y. Cheng. L.-W. Wang, C. Wang, Y.-K. Hu, T.-J. Hou, and M. Lee, "Implementation of Digital HDTV Video Decoder by Multiple Multimedia Video Processors," IEEE Trans. on Consumer Electronics, vol. 42, no. 3, 1996, pp. 395-401.
O. Duardo, S. Hsieh, L. Wu, J. Boo, A. Khurjekar, R. Hingorani, P. Wilford, B. Bolton, H. Morinaka, K. Okada, S. Hosotani, T. Sumi, P. DaGraca, H. Yamamoto, and T. Poon, "An HDTV Video Coder IC for ATV Receivers," IEEE Trans. on Consumer Electronics, vol. 43, no. 3, 1997, pp. 628-632.
Z. Yu, S. Yu, M. Chu, and G. Tian, "Design and Implementation of HDTV Source Decoder," IEEE Trans. on Consumer Electronics, vol. 44, no. 2, 1998, pp. 384-387.
J.-M. Kim and S.-I. Chae, "A Cost-Effective Architecture for HDTV Video Decoder in ATSC Receivers," IEEE Trans. on Consumer Electronics, vol. 44, no. 4, 1998, pp. 1353-1359.
H. Wang, X. Mao, and L. Yu, "A Novel HDTV Video Decoder and Decentralized Control Scheme," IEEE Trans. on Consumer Electronics, vol. 47, no. 4, 2001, pp. 723-728.
C.L. Lee, "Parallel Implementation of Motion-Compensation for HDTV Video Decoder," IEEE Trans. on Consumer Electronics, vol. 44, no. 2, 1998, pp. 251-255.
J.-H. Li and N. Ling, "Architecture and Bus-Arbitration Schemes for MPEG-2 Video Decoder," IEEE Trans. on Circuits and Systems for Video Technology, vol. 9, no. 5, 1999, pp. 727-736. 306 Ling and Wang
H. Geib, S.J. Prange, and C.v. Reventlow, "Reducing Memory in MPEG-2 Video Decoder Architectures," IEEE International Conference on Consumer Electronics, 1997, pp. 176-177.
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Ling, N., Wang, NT. A Real-Time Video Decoder for Digital HDTV. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 33, 295–306 (2003). https://doi.org/10.1023/A:1022179914445
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DOI: https://doi.org/10.1023/A:1022179914445