Abstract
Cellular Carry Lookahead (CLA) adders are systematically implemented in arithmetic units due to their regular, well-balanced structure. In terms of testability and with respect to the classical Cell Fault Model (CFM), cellular CLA adders have poor testability by construction. Design-for-testability (DFT) modifications for cellular CLA adders have been proposed in the literature providing complete CFM testability making the adders either level-testable or C-testable. These designs impose significant area and performance overheads. In this paper, we propose DFT modifications for cellular CLA adders to achieve complete CFM testability with special emphasis on the minimum impact in terms of area and performance. Complete CFM testability is achieved without adding any extra inputs to the adder, with very small area and performance overheads, thus providing a practical solution. The proposed DFT scheme requires only 1 extra output and it is not necessary to put the circuit in a special test mode, while the earlier schemes require the addition of 2 extra inputs to set the circuit in test mode. A rigorous proof of the linear-testability of the adder is given and a sufficient linear-sized test set is provided that guarantees 100% CFM fault coverage. Surprisingly, the size of the proposed linear-sized test set is, in most practical cases, comparable or even smaller than a logarithmic-sized test set proposed in the literature.
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References
T. Lynch and E.E. Swartzlander, “A Spanning Tree Carry Lookahead Adder,” IEEE Transactions on Computers, vol. 41, no. 8, pp. 931-939, Aug. 1992.
W.H. Kautz, “Testing for Faults in Cellular Logic Arrays,” in Proc. 8th Annual Symposium Switching and Automata Theory, 1967, pp. 161-174.
R.D. Blanton and J.P. Hayes, “Design of a Fast, Easily Testable ALU,” in Proc. of the 14th IEEE VLSI Test Symposium, 1996, pp. 9-16.
R.D. Blanton and J.P. Hayes, “Testability of Convergent Tree Circuits,” IEEE Transactions on Computers, vol. 45, no. 8, pp. 950-963, Aug. 1996.
D. Gizopoulos, A. Paschalis, and Y. Zorian, “Effective Built-In Self-Test for Booth Multipliers,” IEEE Design & Test of Computers, vol. 15, no. 3, pp. 105-111, July-Sept. 1999.
D. Gizopoulos, A. Paschalis, and Y. Zorian, “An Effective Built-In Self-Test Scheme for Array Multipliers,” IEEE Transactions on Computers, vol. 48, no. 9, pp. 936-950, Sept. 1999.
A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, and Y. Zorian, “An Effective BIST Architecture for Fast Multiplier Cores,” in Proc. IEEE Design Automation and Test in Europe Conference, 1999, pp. 117-121.
D. Gizopoulos, A. Paschalis, and Y. Zorian, “An Effective BIST Scheme for Datapaths,” in Proc. IEEE International Test Conference, 1996, pp. 76-85.
A.D. Friedman, “A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays,” IEEE Transactions on Computers, vol. 43, no. 12, pp. 1365-1375, Dec. 1994.
J.P. Shen and F.J. Ferguson, “The Design of EasilyTestable VLSI Array Multipliers,” IEEE Transactions on Computers, vol. 33, no. 6, pp. 554-560, June 1984.
C. Wu and P.R. Cappello, “Easily Testable Iterative Logic Arrays,” IEEE Transactions on Computers, vol. 39, no. 5, pp. 640–652, May 1990.
R.D. Blanton and J.P. Hayes, “Testability Properties of Divergent Trees,” Journal of Electronic Testing: Theory and Applications, vol. 11, no. 3, pp. 197-209, Dec. 1997.
W.P. Marnane and W.R. Moore, “Testing VLSI Regular Arrays,” Journal of Electronic Testing: Theory and Applications, vol. 6, no. 2, pp. 153-177, April 1995.
M. Psarakis, D. Gizopoulos, and A. Paschalis, “Test Generation and Fault Simulation for Cell Fault Model Using Stuckat Fault Model Based Test Tools,” Journal of Electronic Testing: Theory and Applications, vol. 13, no. 3, pp. 315-319, Dec. 1998.
R.D. Blanton and J.P. Hayes, “On the Design of Fast, Easily Testable ALUs,” IEEE Transactions on VLSI Systems, vol. 8, no. 2, pp. 220-223, April 2000.
B. Becker and U. Sparmann, “Regular Structures and Testing: RCC Adders,” 3rd Worskhop on Parallel Computation and VLSI Theory (AWOC), Lecture Notes in Computer Science 319, Springer-Verlag, June/July 1988, pp. 288-300.
B. Becker and U. Sparmann, “Computations over Finite Monoids and their Test Complexity,” in Proc. of the 19th Fault-Tolerant Computing Symposium (FTCS), June 1989, pp. 299–306.
R.D. Blanton and J.P. Hayes, “Properties of the Input Pattern Fault Model,” in Proc. of the International Conference on Computer Design (ICCD) 1997, Oct. 1997.
Advanced Micro Devices Inc., Am29050 Processor Datasheet, December 1994, “http://www.amd.com/products/lpd/techdocs/ 29k/050 ds.pdf”.
Austria Mikro Systeme International, “2.0-Micron, 1.2-Micron, 1.0-Micron and 0.8-Micron Standard Cell Databook”, 1995.
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Gizopoulos, D., Psarakis, M., Paschalis, A. et al. Easily Testable Cellular Carry Lookahead Adders. Journal of Electronic Testing 19, 285–298 (2003). https://doi.org/10.1023/A:1023749030268
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DOI: https://doi.org/10.1023/A:1023749030268